Abstract: A high speed buffer memory interface for connecting network and host devices provides dual paths of buffering where data travels via an input buffer or output buffer and instructions about the transfer of that data travel via a receive buffer and command buffer. The microprocessor reads instructions from the receive buffer placed there by the network interface circuitry and writes instructions to the command buffer to be read by the network interface circuitry without need to precisely synchronize with the input and network interface circuitry as would require time consuming, interrupt-type transactions.

Abstract: A dual-port, static random access memory (DPSRAM) is configured as a virtual first-in-first-out (FIFO) register under the control of a microprocessor executing a stored program or similar circuit to allow both for conventional random access data buffering between the data source and the data receiver and FIFO-type data buffering in which the data source and data receiver need not generate an address for each data word transferred, but these addresses may be automatically generated in sequence by the buffer using special circuitry.

Abstract: A method and apparatus for improving sustainable data throughput between a host system minicomputer and a plurality of peripheral memories utilizes a dual-ported RAM memory, a microelectronic processor with an instruction rate of 10 MIPS or greater and task switching firmware executed by the microelectronic processor for rapid switching between communication on a peripheral data bus to the peripheral memories and communication on a system data bus having a relatively higher data rate. Also disclosed is a method of data caching on the host system using the peripheral controller.