Abstract: A nonvolatile semiconductor memory device is provided which includes: a P-type memory cell transistor having a source, a drain, a gate, and a charge storage layer; and a control circuit which, in a case where the P-type memory cell transistor has its threshold greater than or equal to a first value (Vr) and less than or equal to a second value (Vrd), carries out a program operation of injecting electrons into the charge storage layer.

Abstract: According to an aspect of the present invention, it is provided: a nonvolatile semiconductor memory device comprising: a plurality of bit lines arranged in a first direction; a plurality of source lines arranged in the first direction, the plurality of source lines being parallel to the plurality of bit lines, the plurality of source lines being distinct from the plurality of bit lines; a plurality of memory gate lines arranged in a second direction perpendicular to the first direction; a plurality of memory cells arranged in a matrix, each of the plurality of memory cells including a p type MIS nonvolatile transistor having a first terminal, a second terminal, a channel between the first terminal and the second terminal, a gate insulation film formed on the channel, a gate electrode connected to one corresponding memory gate line of the plurality of memory gate lines, and a carrier storage layer formed between the gate insulation film and the gate electrode, the first terminal being connected to one correspo

Abstract: A hot electron (BBHE) is generated close to a drain by tunneling between bands, and it data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain voltage, a relation of Vg>Vsub>Vs>Vd is satisfied, Vg?Vd is a value of a potential difference required for generating a tunnel current between the bands or higher, and Vsub?Vd is substantially equivalent to a barrier potential of the tunnel insulating film or higher.

Abstract: A non-volatile semiconductor device includes an n type well formed in a semiconductor substrate having a surface, the surface having a plurality of stripe shaped grooves and a plurality of stripe shaped ribs, a plurality of stripe shaped p type diffusion regions formed in upper parts of each of the plurality of ribs, the plurality of stripe shaped p type diffusion regions being parallel to a longitudinal direction of the ribs, a tunneling insulation film formed on the grooves and the ribs, a charge storage layer formed on the tunneling insulating film, a gate insulation film formed on the charge storage layer, and a plurality of stripe shaped conductors formed on the gate insulating film, the plurality of stripe shaped conductors arranged in a direction intersecting the longitudinal direction of the ribs with a predetermined interval wherein an impurity diffusion structure in the ribs are asymmetric.

Abstract: According to an aspect of the present invention, it is provided: a nonvolatile semiconductor memory device comprising: a plurality of bit lines arranged in a first direction; a plurality of source lines arranged in the first direction, the plurality of source lines being parallel to the plurality of bit lines, the plurality of source lines being distinct from the plurality of bit lines; a plurality of memory gate lines arranged in a second direction perpendicular to the first direction; a plurality of memory cells arranged in a matrix, each of the plurality of memory cells including a p type MIS nonvolatile transistor having a first terminal, a second terminal, a channel between the first terminal and the second terminal, a gate insulation film formed on the channel, a gate electrode connected to one corresponding memory gate line of the plurality of memory gate lines, and a carrier storage layer formed between the gate insulation film and the gate electrode, the first terminal being connected to one correspo

Abstract: A replica circuit includes: a first conductivity type first transistor; a first current path including a first conductivity type second transistor and a second conductivity type third transistor; a second current path including a first conductivity type fourth transistor configured so that current equivalent to a current flowing through the first transistor flows through the fourth transistor, and a second conductivity type fifth transistor configured so that current equivalent to a current flowing through the third transistor flows through the fifth transistor, the fourth transistor and the fifth transistor being connected in series; a second conductivity type sixth transistor configured so a current equivalent to a current flowing through the third transistor flows through the sixth transistor; a first control configured to supply a reference voltage to the drain of the first transistor; and a second control configured to supply the reference voltage to the drain of the fourth transistor.

Abstract: According to an aspect of the present invention, it is provided: a nonvolatile semiconductor memory device comprising: a plurality of bit lines arranged in a first direction; a plurality of source lines arranged in the first direction, the plurality of source lines being parallel to the plurality of bit lines, the plurality of source lines being distinct from the plurality of bit lines; a plurality of memory gate lines arranged in a second direction perpendicular to the first direction; a plurality of memory cells arranged in a matrix, each of the plurality of memory cells including a p type MIS nonvolatile transistor having a first terminal, a second terminal, a channel between the first terminal and the second terminal, a gate insulation film formed on the channel, a gate electrode connected to one corresponding memory gate line of the plurality of memory gate lines, and a carrier storage layer formed between the gate insulation film and the gate electrode, the first terminal being connected to one correspo

Abstract: According to an one aspect of the present invention, it is provided a non-volatile semiconductor memory device comprising: a first N type well; a plurality of P type non-volatile memory cells arranged in matrix and formed in the N type well; a plurality of sub-bit lines, each of the sub-bit lines being connected to drains of the P type non-volatile memory cells in a respective one of columns of the matrix; a first P type well; and a plurality of N type selection transistors, each of the selection transistors selectively connecting a respective one of sub-bit lines to a corresponding one of main bit lines.

Abstract: A non-volatile semiconductor device includes an n type well formed in a semiconductor substrate having a surface, the surface having a plurality of stripe shaped grooves and a plurality of stripe shaped ribs, a plurality of stripe shaped p type diffusion regions formed in upper parts of each of the plurality of ribs, the plurality of stripe shaped p type diffusion regions being parallel to a longitudinal direction of the ribs, a tunneling insulation film formed on the grooves and the ribs, a charge storage layer formed on the tunneling insulating film, a gate insulation film formed on the charge storage layer, and a plurality of stripe shaped conductors formed on the gate insulating film, the plurality of stripe shaped conductors arranged in a direction intersecting the longitudinal direction of the ribs with a predetermined interval wherein an impurity diffusion structure in the ribs are asymmetric.

Abstract: A hot electron (BBHE) is generated close to a drain by tunneling between bands, and it data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain voltage, a relation of Vg>Vsub>Vs>Vd is satisfied, Vg?Vd is a value of a potential difference required for generating a tunnel current between the bands or higher, and Vsub?Vd is substantially equivalent to a barrier potential of the tunnel insulating film or higher.

Abstract: A semiconductor device can be manufactured with a high non-defect ratio, making it possible to easily guarantee the KGD (Known-Good-Die) of semiconductor chips, when configuring one packaged semiconductor device on which a plurality of semiconductor chips is mounted. Utilizing each semiconductor chip is made possible without limits on terminal position, pitch, signal arrangement, and so on. Protrusions provided to a semiconductor chip mounted sealing sub-board are attached to a package substrate. A plurality of semiconductor bare chips is disposed in a space formed between the semiconductor chip mounted sealing sub-board and the package substrate, making wiring possible.

Abstract: A hot electron (BBHE) is generated close to a drain by tunneling between bands, and it data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain voltage, a relation of Vg>Vsub>Vs>Vd is satisfied, Vg?Vd is a value of a potential difference required for generating a tunnel current between the bands or higher, and Vsub?Vd is substantially equivalent to a barrier potential of the tunnel insulating film or higher.

Abstract: A nonvolatile semiconductor memory device includes a first PMOS transistor and a second PMOS transistor having a gate, the first and the second PMOS transistors being connected in series; and a first NMOS transistor and a second NMOS transistor having a gate, the first and the second NMOS transistors being connected in series; wherein the gate of the second PMOS transistor and the gate of the second NMOS transistor are commonly connected and floated.

Abstract: An object of this invention is to provide a rewritable nonvolatile memory cell that can have a wide reading margin, and can control both a word line and a bit line by changing the level of Vcc. As a solution, a flip-flop is formed by cross (loop) connect of inverters including memory transistors that can control a threshold voltage by charge injection into the side spacer of the transistors. In the case of writing data to one memory transistor, a high voltage is supplied to a source of the memory transistor through a source line and a high voltage is supplied to a gate of the memory transistor through a load transistor of the other side inverter. In the case of erasing the written data, a high voltage is supplied to the source of the memory transistor through the source line.

Abstract: The present invention relates to a nonvolatile semiconductor memory, and more specifically relates to a nonvolatile semiconductor memory with increased program throughput. The present invention provides a nonvolatile semiconductor memory device with a plurality of block source lines corresponding to the memory blocks, arranged in parallel to the word lines, a plurality of global source lines arranged in perpendicular to the block source lines; and a plurality of switches for selectively connecting corresponding ones of the block source lines and the global source lines.

Abstract: The present invention relates to a nonvolatile semiconductor memory, and more specifically relates to a nonvolatile semiconductor memory with increased program throughput. The present invention provides a nonvolatile semiconductor memory device with a plurality of block source lines corresponding to the memory blocks, arranged in parallel to the word lines, a plurality of global source lines arranged in perpendicular to the block source lines; and a plurality of switches for selectively connecting corresponding ones of the block source lines and the global source lines.

Abstract: A hot electron (BBHE) is generated close to a drain by tunneling between bands, and bit data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain voltage, a relation of Vg>Vsub>Vs>Vd is satisfied, Vg?Vd is a value of a potential difference required for generating a tunnel current between the bands or higher, and Vsub?Vd is substantially equivalent to a barrier potential of the tunnel insulating film or higher.

Abstract: According to an aspect of the present invention, it is provided: a nonvolatile semiconductor memory device comprising: a plurality of bit lines arranged in a first direction; a plurality of source lines arranged in the first direction, the plurality of source lines being parallel to the plurality of bit lines, the plurality of source lines being distinct from the plurality of bit lines; a plurality of memory gate lines arranged in a second direction perpendicular to the first direction; a plurality of memory cells arranged in a matrix, each of the plurality of memory cells including a p type MIS nonvolatile transistor having a first terminal, a second terminal, a channel between the first terminal and the second terminal, a gate insulation film formed on the channel, a gate electrode connected to one corresponding memory gate line of the plurality of memory gate lines, and a carrier storage layer formed between the gate insulation film and the gate electrode, the first terminal being connected to one correspo

Abstract: A hot electron (BBHE) is generated close to a drain by tunneling between bands, and bit data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain voltage, a relation of Vg>Vsub>Vs>Vd is satisfied, Vg?Vd is a value of a potential difference required for generating a tunnel current between the bands or higher, and Vsub?Vd is substantially equivalent to a barrier potential of the tunnel insulating film or higher.

Abstract: A semiconductor device can be manufactured with a high non-defect ratio, making it possible to easily guarantee the KGD (Known-Good-Die) of semiconductor chips, when configuring one packaged semiconductor device on which a plurality of semiconductor chips is mounted. Utilizing each semiconductor chip is made possible without limits on terminal position, pitch, signal arrangement, and so on. Protrusions provided to a semiconductor chip mounted sealing sub-board are attached to a package substrate. A plurality of semiconductor bare chips is disposed in a space formed between the semiconductor chip mounted sealing sub-board and the package substrate, making wiring possible.