Abstract: A serial isolated communication method, applied to a transmitter of a serial isolated communication system, includes: obtaining isolated communication data to be transferred; encoding isolated communication data with more than two bits into corresponding data pulse signals according to a preset encoding rule, wherein a group of data pulse signals include a positive pulse, a negative pulse, and a delay of 0 or N pulse widths between the positive pulse and the negative pulse, and N?1; and transferring the data pulse signals to a receiver. A serial isolated communication method, applied to a receiver of a serial isolated communication system, includes: receiving data pulse signals transferred from a transmitter; decoding the data pulse signals into the isolated communication data according to a preset decoding rule; and obtaining the isolated communication data. Serial isolated communication device and system are further provided.

Abstract: A serial isolated communication method, applied to a transmitter of a serial isolated communication system, includes: obtaining isolated communication data to be transferred; encoding isolated communication data with more than two bits into corresponding data pulse signals according to a preset encoding rule, wherein a group of data pulse signals include a positive pulse, a negative pulse, and a delay of 0 or N pulse widths between the positive pulse and the negative pulse, and N?1; and transferring the data pulse signals to a receiver. A serial isolated communication method, applied to a receiver of a serial isolated communication system, includes: receiving data pulse signals transferred from a transmitter; decoding the data pulse signals into the isolated communication data according to a preset decoding rule; and obtaining the isolated communication data. Serial isolated communication device and system are further provided.

Abstract: A transistor switching circuit and an integrated circuit thereof are provided. The transistor switching circuit includes: at least two transistors M1 and M2, and a voltage follower. The gate of the transistor M1 and the gate of the transistor M2 are connected to a first node G, the first node G is connected to a first current source, and the source of the transistor M1 and the source of the transistor M2 are connected to a second node S1. The voltage follower includes a transistor M3 and a second current source. The gate of the transistor M3 is connected to the second node S1, and the source of the transistor M3 is connected to the second current source. One end of a resistive device is connected to the source of the transistor M3, and another end of the resistive device is connected to the first node G.