Patents Assigned to Georgia Tech Research
  • Publication number: 20130278295
    Abstract: An apparatus for measuring a high speed signal may comprise a plurality of Analog-Digital converters (AD converter) that are arranged in parallel to each other to sample an input signal at different frequencies; a plurality of frequency synthesizers configured to provide each AD converter with a different sampling frequency; a signal processor configured to receive an output of the plurality of AD converters to reconstruct the input signal; and/or a controller configured to receive and process a trigger signal.
    Type: Application
    Filed: February 19, 2013
    Publication date: October 24, 2013
    Applicants: GEORGIA TECH RESEARCH CORPORATION, SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung Yeol KIM, Hyun Woo CHOI, Nicholas TZOU, Xian WANG, Thomas MOON, Abhijit CHATTERJEE, Ho Sun YOO
  • Patent number: 8566928
    Abstract: A system and method for detecting a first network of compromised computers in a second network of computers, comprising: collecting Domain Name System (DNS) data for the second network; examining the collected data relative to DNS data from known comprised and/or uncompromised computers in the second network; and determining the existence of the first network and/or the identity of compromised computers in the second network based on the examination.
    Type: Grant
    Filed: October 3, 2006
    Date of Patent: October 22, 2013
    Assignee: Georgia Tech Research Corporation
    Inventors: David Dagon, Nick Feamster, Wenke Lee, Robert Edmonds, Richard Lipton, Anirudh Ramachandran
  • Patent number: 8564435
    Abstract: Various sensors, systems, and methods for monitoring environmental conditions are provided. In one embodiment, among others, a passive sensor includes an antenna; a modulating circuit coupled to the antenna by a microstrip transmission line, the modulating circuit capable of modulating a backscattered signal; a sensing material disposed between the microstrip transmission line and a ground plane of the passive sensor, where an electrical property of at least a portion of the sensing material varies with the environmental condition; and where the modulated backscattered signal includes at least one of phase and amplitude information corresponding to the electrical property of the portion of the sensing material.
    Type: Grant
    Filed: June 24, 2009
    Date of Patent: October 22, 2013
    Assignee: Georgia Tech Research Corporation
    Inventors: Gregory David Durgin, Andrew F. Peterson, Azhar Hason
  • Patent number: 8565117
    Abstract: A network may include a plurality of nodes forming a first layer and a sub-set of the plurality of nodes forming a second layer. The first layer may follow a first routing objective in routing traffic, and the second layer may develop constraints based on the first routing objective and follow a second routing objective within the developed constraints in routing traffic. In another network, the second layer may follow a second routing objective in routing traffic, and the first layer may develop constraints based on the second routing objective and follow a first routing objective within the developed constraints in routing traffic.
    Type: Grant
    Filed: January 15, 2008
    Date of Patent: October 22, 2013
    Assignees: Alcatel Lucent, Georgia Tech Research Corporation
    Inventors: Volker Friedrich Hilt, Markus Andreas Hofmann, Srinivasan Seetharaman, Mostafa H. Ammar
  • Patent number: 8563365
    Abstract: An exemplary embodiment of the present invention provides a chip for use in fabricating a three-dimensional integrated circuit, the chip comprising a wafer, one or more metallic-filled, electrical vias, and one or more hollow, fluidic vias. The wafer can comprise a first surface and a second surface. The one or more metallic-filled, electrical vias can extend through the wafer. Each electrical via can be in electrical communication with an electrical interconnect proximate the first surface, providing electrical communication between chips in the integrated circuit. The one or more hollow, fluidic vias can extend through the wafer. Each fluidic via can be in fluid communication with a fluidic interconnect, providing fluid communication between adjacent chips in the integrated circuit. Each fluidic interconnect can comprise a first end proximate the first surface, a second end, and a cap proximate the second end, defining an air-filled space within the fluidic interconnect.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: October 22, 2013
    Assignee: Georgia Tech Research Corporation
    Inventors: Calvin Richard King, Jr., Jesal Zevari, James D. Meindl, Muhannad S. Bakir
  • Patent number: 8562806
    Abstract: Improved electrochemical biosensor arrays and instruments are disclosed herein. Methods of making and using the electrochemical biosensor instruments are also disclosed. An electrochemical biosensor array can include an array of microelectrodes disposed on a substrate. Each microelectrode can include a conducting electrode material disposed on a portion of the substrate, a first polymeric layer disposed on at least a portion of the conducting electrode material, a second polymeric layer disposed on at least a portion of the first polymeric layer, and a capture molecule that is in physical communication with the second polymeric layer.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: October 22, 2013
    Assignee: Georgia Tech Research Corporation
    Inventors: Jiri Janata, Miroslava Josowicz, George Yang Yu
  • Publication number: 20130270695
    Abstract: The various embodiments of the present invention provide a stress-relieving, second-level interconnect structure that is low-cost and accommodates TCE mismatch between low-TCE packages and PCBs. The various embodiments of the interconnect structure are reworkable and can be scaled to pitches from about 1 millimeter (mm) to about 150 micrometers (?m). The interconnect structure comprises at least a first pad, a supporting pillar, and a solder bump, wherein the first pad and supporting pillar are operative to absorb substantially all plastic strain, therefore enhancing compliance between the two electronic components. The versatility, scalability, and stress-relieving properties of the interconnect structure of the present invention make it a desirable structure to utilize in current two-dimensional and ever-evolving three-dimensional IC structures.
    Type: Application
    Filed: September 20, 2011
    Publication date: October 17, 2013
    Applicant: Georgia Tech Research Corporation
    Inventors: Pulugurtha Markondeya Raj, Nitesh Kumbhat, Venky Sundaraman, Rao R. Tummala, Xian Qin
  • Publication number: 20130270534
    Abstract: A field-effect transistor includes a gate, a source and a drain; a semiconductor layer between the source and the drain; and a gate insulator between the gate and the semiconductor layer. The gate insulator comprises a first layer adjoining the semiconductor layer; and a second layer. The first layer is formed from an amorphous fluoropolymer having a first dielectric constant and a first thickness. The second layer has a second dielectric constant and a second thickness. The first dielectric constant is smaller than 3, the first thickness is smaller than 200 nm, the second dielectric constant is higher than 5, and the second thickness is smaller than 500 nm.
    Type: Application
    Filed: October 5, 2011
    Publication date: October 17, 2013
    Applicant: GEORGIA TECH RESEARCH CORPORATION
    Inventors: Do Kyung Hwang, Jungbae Kim, Canek Fuentes-Hernandez, Bernard Kippelen
  • Patent number: 8558329
    Abstract: A device includes a substrate having a first surface. A piezoelectric nanowire is disposed on the first surface of the substrate. The piezoelectric nanowire has a first end and an opposite second end. The piezoelectric nanowire is subjected to an amount of strain. A first Schottky contact is in electrical communication with the first end of the piezoelectric nanowire. A second Schottky contact is in electrical communication with the second end of the piezoelectric nanowire. A bias voltage source is configured to impart a bias voltage between the first Schottky contact and the second Schottky contact. A mechanism is configured to measure current flowing through the piezoelectric nanowire. The amount of strain is selected so that a predetermined current will flow through the piezoelectric nanowire when light of a selected intensity is applied to a first location on the piezoelectric nanowire.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: October 15, 2013
    Assignee: Georgia Tech Research Corporation
    Inventors: Zhong L. Wang, Youfan Hu, Yan Zhang
  • Patent number: 8559544
    Abstract: Disclosed herein are lattice reduction systems and methods for a MIMO communication system. One such method includes providing a channel matrix corresponding to a channel in a MIMO communication system, preprocessing the channel matrix to form at least an upper triangular matrix, implementing a relaxed size reduction process, and implementing a basis update process. Implementing the relaxed size reduction process comprises choosing a first relaxed size reduction parameter for a first-off-diagonal element of the upper triangular matrix, choosing a second relaxed size reduction parameter, which is greater than the first relaxed size reduction parameter, for a second-off-diagonal element of the upper triangular matrix evaluating whether a first relaxed size reduction condition is satisfied for the first-off-diagonal element of the upper triangular matrix, and evaluating whether a second relaxed size reduction condition is satisfied for the second-off-diagonal element of the upper triangular matrix.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: October 15, 2013
    Assignee: Georgia Tech Research Corporation
    Inventors: David Verl Anderson, Brian Joseph Gestner, Wei Zhang, Xiaoli Ma
  • Patent number: 8546930
    Abstract: Three dimensional integrated circuits with double sided power, coolant, and data features and methods of constructing same are provided. According to some embodiments, an integrated circuit package can generally comprise one or more semiconductor wafers and opposing end substrates. The semiconductor wafers can each have a top exterior surface and a bottom exterior surface. The plurality of semiconductor wafers can form a multi-dimensional wafer stack of die wafers such that adjacent wafers have facing surfaces. Each of the semiconductor wafers can comprise one or more channels formed through the wafers. A portion of the channels can extend generally between the top and bottom exterior surfaces of the semiconductor wafers. A portion of the channels can carry conductors for coupling the wafers and/or coolant for cooling the wafers. The opposing end substrates can be disposed proximate opposing ends of the multi-dimensional stack.
    Type: Grant
    Filed: January 26, 2010
    Date of Patent: October 1, 2013
    Assignee: Georgia Tech Research Corporation
    Inventors: Muhannad S. Bakir, Gang Huang
  • Patent number: 8546505
    Abstract: This invention relates generally to norbornene-monomer, poly(norbornene)homopolymer, and poly(norbornene)copolymer compounds containing a functionalized carbazole side chain, having desirable solution processability and host characteristics. It also relates to hole transport and/or electron blocking materials, and to organic host materials for an organic luminescence layer, an OLED device, and compositions of matter which include these compounds.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: October 1, 2013
    Assignee: Georgia Tech Research Corporation
    Inventors: Yadong Zhang, Seth Marder, Carlos Zuniga, Stephen Barlow, Bernard Kippelen, Andreas Haldi, Benoit Domerq, Marcus Weck, Alpay Kimyonok
  • Patent number: 8545606
    Abstract: The present invention relates to a method for treating molecular sieve particles for use in a mixed matrix membrane useful in, for example, gas separations. Membranes employing treated molecular sieve particles may exhibit enhanced permeabilities and selectivities in regard to, for example, the separation of carbon dioxide and methane.
    Type: Grant
    Filed: August 20, 2010
    Date of Patent: October 1, 2013
    Assignee: Georgia Tech Research Corporation
    Inventors: William John Koros, Jason Keith Ward
  • Publication number: 20130254149
    Abstract: An affective model device and a method of deciding the behavior of an affective model device are provided. The affective model device has affective components representing trait, attitude, mood, emotion, and the like. The affective model device updates the emotion at regular time intervals or when a stimulus is received, and decides the behavior based on the updated emotion. The emotion may be updated depending on trait, attitude, and mood.
    Type: Application
    Filed: May 17, 2013
    Publication date: September 26, 2013
    Applicants: Georgia Tech Research Corporation, Samsung Electronics Co., Ltd.
    Inventors: Hyun-Ryong JUNG, Jamee Kim LEE, Lilia MOSHKINA, Ronald ARKIN, Sunghyun PARK, Chien-Ming HUANG
  • Publication number: 20130252307
    Abstract: The invention provides a method for increasing the stability and/or activity of a polypeptide at low pH and/or elevated temperatures. The invention further provides a method for increasing the melting temperature of a polypeptide. Also provided are paleoenzymologically reconstructed thioredoxin polypeptides having activity at higher temperatures and/or lower pH than extant thioredoxin polypepetides, as well as paleoenzymologically reconstructed thioredoxin polypeptides having higher melting temperatures than extant thioredoxin polypepetides.
    Type: Application
    Filed: July 15, 2011
    Publication date: September 26, 2013
    Applicant: GEORGIA TECH RESEARCH CORPORATION
    Inventors: Julio M. Fernandez, Raul Perez-Jimenez, Eric Gaucher, Pallav Kosuri
  • Patent number: 8542618
    Abstract: Devices, systems, and methods of improving protocol performance are disclosed. One method includes transmitting a block of frames to another communication device, and upon completion of the transmitting, requesting an acknowledgement of the transmitted block from the another communication device. The method further includes receiving the acknowledgement and adjusting the number of frames in the block based on information from the received acknowledgement.
    Type: Grant
    Filed: November 14, 2007
    Date of Patent: September 24, 2013
    Assignee: Georgia Tech Research Corporation
    Inventors: Raghupathy Sivakumar, Yeonsik Jeong, Sandeep Kakumanu, Cheng-Lin Tsao
  • Publication number: 20130245137
    Abstract: Catalyst compositions comprising molybdenum, sulfur and an alkali metal ion supported on a nanofibrous, mesoporous carbon molecular sieve are useful for converting syngas to higher alcohols. The compositions are produced via impregnation and may enhance selectivity to ethanol in particular.
    Type: Application
    Filed: December 1, 2011
    Publication date: September 19, 2013
    Applicant: Georgia Tech Research Corporation
    Inventors: Christopher W. Jones, Pradeep K. Agrawal, Tien Thao Nguyen
  • Publication number: 20130243876
    Abstract: The present invention provides a method of treating an ovarian cancer, the method comprising delivering one or more miR-200 family members to a mammalian subject in need thereof in an amount effective to treat the ovarian cancer. Also provided are methods of preventing metastasis of an ovarian cancer, the method comprising delivering one or more miR-200 family members to a mammalian subject in need thereof in an amount effective to prevent metastasis. Further provided are methods of sensitizing an ovarian cancer to a cytotoxic therapy, the method comprising delivering one or more miR-200 family members to a mammalian subject in need thereof in an amount effective to sensitize the ovarian cancer to the cytotoxic therapy. The invention also contemplates methods of reducing epithelial-to-mesenchymal transition (EMT) in an ovarian cancer or cancer cell as well as methods of inducing mesenchymal-to-epithelial transition (MET).
    Type: Application
    Filed: November 23, 2011
    Publication date: September 19, 2013
    Applicant: Georgia Tech Research Corporation
    Inventors: John McDonald, Nathan John Bowen, LiJuan Wang
  • Publication number: 20130244408
    Abstract: Systems and methods for MBE growing of group-III Nitride alloys, comprising establishing an average reaction temperature range from about 250 C to about 850 C; introducing a nitrogen flux at a nitrogen flow rate; introducing a first metal flux at a first metal flow rate; and periodically stopping and restarting the first metal flux according to a first flow duty cycle. According to another embodiment, the system comprises a nitrogen source that provides nitrogen at a nitrogen flow rate, and, a first metal source comprising a first metal effusion cell that provides a first metal at a first metal flow rate, and a first metal shutter that periodically opens and closes according to a first flow duty cycle to abate and recommence the flow of the first metal from the first metal source. Produced alloys include AlN, InN, GaN, InGaN, and AlInGaN.
    Type: Application
    Filed: November 8, 2011
    Publication date: September 19, 2013
    Applicant: GEORGIA TECH RESEARCH CORPORATION
    Inventors: Michael William Moseley, William Alan Doolittle
  • Publication number: 20130245328
    Abstract: Catalyst compositions for production of higher alcohols comprise a hydrotalcite or hydrotalcite-like support impregnated with molybdenum and an alkali metal. When the compositions are used to convert syngas, selectivity to higher (C2+) alcohols is increased in comparison to conversions accomplished over many other catalyst systems.
    Type: Application
    Filed: December 1, 2011
    Publication date: September 19, 2013
    Applicant: Georgia Tech Research Corporation
    Inventors: Christopher W. Jones, Pradeep K. Agrawal, Tien Thao Nguyen