Abstract: A charge pump device with NMOS transistor circuit is provided for low voltage operation. The charge pump stage, comprising four NMOS transistors and three capacitors, is configured to alleviate the substrate body effect and the charge transfer loss. The charge pump circuit can be constructed on a p-type semiconductor substrate directly without deep N well isolation. The circuit is driven by two non-overlapping complementary clock signals, which can be generated easily with an integrated fabrication. The charge pump device can be implemented with a multiple stage to provide a stable high voltage output.

Abstract: The present invention relates to a device and method for driving an under damped voice coil motor (VCM) actuator of a camera lens. In one embodiment, the device for driving an under damped VCM actuator comprises a first generator operable to read a first manufacture data from an image signal processor (ISP) and to generate a half natural period, ½ Td, of the VCM actuator by selecting a value approximate to the first data in a first table of the device, a second generator operable to read a second manufacture data from the ISP and to generate the maximum overshoot, K, of the VCM actuator by selecting a value approximate to the second data in a second table of the device, an input shaping signal generator operable to read an input signal corresponding to a desired camera lens moving distance from the ISP and to generate a shaping signal according to the value of the half natural period and the maximum overshoot.

Abstract: A serial memory device having a non-volatile memory array including a plurality of memory blocks, one or more said plurality of blocks being capable of being placed in a locked or an unlocked state upon receiving designated lock or unlock signal sequences is provided. The unlock signal sequences comprises at least two sequential signal sequences: a first unlock sequence, which has 1 to 7 signal bits, is applied to one of address input pins or a logic low enabled write-protection input pin and a second unlock sequence follows the first unlock signal sequence and is applied to a serial data access pin. The memory device further comprising a control logic circuit block coupled to a write-protection circuit block to provide means to identify the designated lock and unlock signal sequences and to set a protection state in a security area.

Abstract: A memory device comprises at least one memory array on a semiconductor substrate. Each said memory array comprises a page control line and a plurality of pages, each said page is arranged in a row comprising a plurality of bytes which couple to a page control transistor with its drain terminal connected to the page control line. Each said byte includes at least one memory cell. Said memory array further comprises a plurality of source control devices which are configured to provide either predetermined biases or floating potentials to source lines, each said source line couples to all the bytes on the same byte segment of the memory array. Read, erase, and program methods are provided to operate said memory devices in byte addressable fashion.

Abstract: A switching power controller circuit comprises a first terminal pin for a high potential of a power supply for the controller circuit, a second terminal pin for providing output of switch drive signals and for receiving feedback signals, and a third terminal pin for receiving external current signals and for a low potential of the power supply. The switching power controller further comprises a clock generator, a pulse width modulation (PWM) generator, a reference generator, a power switch driver, a feedback signal sampler, a PWM comparator and a floating sampler.