Abstract: A voltage down converter 10 for providing a supply voltage and current to a device, such as a semiconductor device. The voltage down converter includes a first circuit 12 that supplies steady state or “DC” current to the device, and a second circuit 14 that supplies the fluctuating or “AC” current to the device. The first circuit 12 includes a first comparator 18 that drives a first transistor P1 to supply most of the steady state current. The second circuit 14 includes a second comparator 20, which is larger than the first comparator 18, and which drives a second transistor P2, which is smaller than the first transistor P1, to supply the fluctuating current to the device. The converter 10 further includes a feedback circuit 16 for controlling the supply voltage.

Abstract: The present invention provides a system and method for testing embedded memories. The present invention logically combines many different embedded memories into one or more large, virtual memory blocks in order to test multiple memories together. The invention defines the X and/or Y address space in all memories in order to cover all memories combined. Compare circuits associated with each memory module are used to compare the data output from each memory cell to an expected value (e.g., to a value that would be expected if the memory cell was operating properly). The invention further uses mask logic to “mask out” any unimplemented address space in each individual memory. The mask logic will always indicate that the comparison or memory test passed when unimplemented addresses are selected. The results of the comparison may be bundled and multiplexed to a test input/output port.

Abstract: The present invention provides data coherent logic for an SRAM device. The present invention utilizes a data strobe signal and an output strobe signal to control data written into and read out of the. SRAM device from an input/output pad. Data coherent logic is designed to resolve timing conflicts between the data and output strobe signals. The logic selectively delays the output strobe signal when a match occurs for data requested in a read operation immediately following a write operation. The delay allows sufficient time for the data to be registered and selected before being outputted from the device.