Abstract: The present invention provides a successive approximation register (SAR) analog-to-digital converter (ADC) and a method of calibrating the SAR ADC, in which each of LSB and MSB capacitor arrays in a DAC can be used to calibrate weights of capacitors in the other capacitor array. This dispenses with the use of a separate calibration DAC resulting in a simpler circuit. The method can be carried out prior to normal operation of the SAR ADC, adding flexibility to initial design of the SAR ADC.

Abstract: A GPIO circuit and a chip are provided. The GPIO circuit includes at least one output driver branch each including output driver transistor. A gate of the output driver transistor is coupled to a respective pre-driver circuit including a conventional pre-driver circuit, a pre-driver transistor and a slow pre-driver (SPD) circuit. An output of the conventional pre-driver circuit is coupled to the gate of the output driver transistor, and a gate of the pre-driver transistor is coupled to a slope control signal. A drain of the pre-driver transistor is coupled to one terminal of the conventional pre-driver circuit. The SPD circuit is coupled between a source and the drain of the pre-driver transistor. In order to output a signal, the SPD circuit is turned on, and the conventional pre-driver circuit is turned on under the control of the signal to be output.

Abstract: Disclosed are a memory and operation method thereof. The memory comprises a memory array and an access interface for external access to the memory array, the access interface comprising at least one data/address multiplexing line. The method comprises: starting a specified fixed-number-random-access mode, in which the memory array can be continuously read or written in response to receiving a fixed number of random access addresses; sequentially receiving the preset fixed number of access addresses via the data/address multiplexing line in succession; sequentially outputting data read in response to the received access addresses in succession via the data/address multiplexing line in the case where the mode indicates read operations, or sequentially receiving data to be written in response to the received access addresses in succession via the data/address multiplexing line in the case where the mode indicates write operations; and ending the mode by receiving an invalid chip enable signal.

Abstract: The present invention provides a system with an MCU and flash memory and a method for DPD control thereof. A new DPD mode (first DPD mode) is provided by simply adding a power supply pin to the MCU. The power supply pin is coupled to a power supply terminal of the flash memory. In a deep power down mode, the flash memory is configured to be entirely powered down, leading to even lower system power consumption than in a conventional DPD mode (second DPD mode).

Abstract: A clock control device for a serial peripheral interface is disposed in a control device. The clock control device includes: a local delay module configured to delay a local clock signal to obtain a first delayed local clock signal; a clock selector configured to select one of the first delayed local clock signal and an external clock signal as a basic clock signal; and a first delay module configured to phase-delay the basic clock signal to obtain a delayed basic clock signal that can be used by the control device as a reception operating clock for sampling an external data signal transmitted by a storage device.

Abstract: The present invention provides an LDO regulator-based power supply circuit and a chip. The LDO regulator-based power supply circuit includes first and second LDO regulators. It also includes a first current monitoring circuit and/or a second current monitoring circuit. When there is a need for switching from operation based on one of the LDO regulators to operation based on the other LDO regulator, feedback factors or reference voltages of two LDO regulators are configured at different values in a simultaneous turn-on interval, in which they are both ON, and a comparison is made with a detected current, allowing adaptive turn-off of the LDO regulator. After this LDO regulator is turned off, the feedback factor or reference voltage of the LDO regulator that is caused to start operation due to switching is adjusted to restore the LDO regulator-based power supply circuit to the same output voltage as prior to the switching.

Abstract: A semiconductor device includes a substrate, a plurality of first electrode structures, a second electrode structure, and a first dielectric layer. The substrate has a capacitor region. The first electrode structures are disposed on a surface of the substrate in the capacitor region and arranged at intervals in a first direction. The second electrode structure is disposed on side surfaces and a top surface of each of the first electrode structures. The first dielectric layer is disposed between the second electrode structure and each of the first electrode structures.

Abstract: The present invention provides an arcing detection method and system, in which an AI model derives an AI score from current data and preliminarily determines whether a current signal of interest is arcing based on a comparison between the AI score and an AI threshold. It preliminarily determines whether the determination is false. These two determination steps enable more accurate arcing detection. When a false determination count becomes greater than or equal to a false determination count threshold, the AI model is retrained and dynamically updated to adapt itself to the current situation. This dispenses with the need for deployment of multiple static AI models in the system, which requires larger storage memory. The AI model can adapt itself to the current situation without needing manual commissioning of parameters, effectively reducing manpower costs. Further, this dispenses with the need for regular interrogation of environmental changes, reducing the system's task overhead.

Abstract: A package structure is provided. The package structure includes a lead frame comprising a paddle and a plurality of pins arranged around the paddle. Above the paddle are disposed at least one metallized structure and at least one die. The die has a plurality of power pads on its front side. The plurality of power pads are connected to the metallized structure by first bonding wires, and the metallized structure is connected to corresponding pins by second bonding wires.

Abstract: Disclosed are a memory and operation method thereof. The memory comprises a memory array and an access interface for external access to the memory array, the access interface comprising at least one data/address multiplexing line. The method comprises: starting a specified random-column-access mode, in which the memory array can be continuously read or written in response to receiving multiple access addresses having a same row address and random column addresses; receiving a common row address and at least one column address via the data/address multiplexing line; outputting data read in response to the received access address via the data/address multiplexing line in the case where the mode indicates read operation, or receiving data to be written in response to the received access address via the data/address multiplexing line in the case where the mode indicates write operation; and ending the random column access mode by receiving an invalid chip-enable-signal.

Abstract: The present invention provides a semiconductor device and a method of fabricating the same, which includes: providing a semiconductor substrate having a first patterned region and a second patterned region and performing floating-gate poly-Si deposition on the semiconductor substrate thereby forming a first poly-Si layer, wherein the first patterned region has a higher feature density than the second patterned region; performing ion implantation on the first poly-Si layer and forming an oxide layer over a top surface of the first poly-Si layer; with the oxide layer in the second patterned region being protected, etching the oxide layer in the first patterned region; performing a CMP process on the first poly-Si layer in the first patterned region and on the oxide layer and the first poly-Si layer in the second patterned region; and forming the semiconductor device on the basis of the first poly-Si layer that has undergone the CMP process.

Abstract: The present invention provides an analog-to-digital converter (ADC), a system-on-chip (SoC) and an electronic control system. In addition to hardware circuits commonly found in conventional ADCs, including a multi-channel input multiplexer, an analog-to-digital conversion (ADC) circuit, a sequence output multiplexer and a sequence data register, the ADC further includes a sequence management circuit and an interrupt generation circuit, which allow the ADC to operate in a streaming access mode, in which it is interrupted only when it has completed the processing of a preset number of sequences. This overcomes the problems with conventional ADCs arising from their frequent interrupts, in particular possible interrupting of a data processing algorithm running on an MCU core due to such frequent interrupts, which may affect real-time control and operation of an electronic system.

Abstract: A channel selection circuit, an analog-to-digital converter (ADC) and a system-on-chip (SoC) are provided. During a sampling phase of an ADC circuit, a substrate voltage of a MOS switch in a selected channel is set to a voltage of analog input signal to which the channel is coupled. This eliminates the body-bias effect of the MOS switch, greatly improving linearity of the channel selection circuit and enabling the ADC to provide the required high speed and high-accuracy and exhibit excellent performance even at a low power supply voltage. Moreover, harmonic distortion around the dominant frequency can be suppressed, enabling the ADC to provide the required high accuracy (e.g., a 16-bit or even higher resolution).

Abstract: A memory controller and an MCU chip are provided by the present application. The memory controller adds a second memory controller to conventional memory controller architecture and is coupled to second NVM storing a backup of content of first NVM in the memory controller. With this arrangement, one more memory access path is established, which takes full advantage of the fast reading characteristics of the first NVM, and once a system bus identifies an error in content read from the first NVM or a problematic address, the second memory controller can automatically read exactly corresponding backup content from the second NVM and provide it on the system bus, or use it to accurately correct the error in the first NVM. This ensures correctness of content that a central processing unit (CPU) or other master on the system bus reads, without interrupting execution of the system's program.

Abstract: A memory controller and an MCU chip are disclosed. The memory controller adds a second memory controller to a conventional memory controller architecture and is coupled to second NVM having first and second backup banks. In order to perform an OTA upgrade, one of the first and second backup banks of the second NVM is used as a default backup bank for supporting execution of an ongoing program of the system, and the other as an OTA upgrade backup bank for supporting OTA upgrade control.

Abstract: A memory controller (MC) and a microcontroller unit (MCU) chip are disclosed. The MC is obtained by adding a smart load control (SLC) module to an MC architecture with an ECC logic module. When a CPU is reading contents from first memory, the ECC logic module can accurately identify soft failure locations and correct 1, 2 or more bit errors, and when errors exceeding the error correction ability of the ECC logic module, the SLC module can select a suitable error correction mode for handling the soft failures in the first memory based on conditions of different ECC errors and soft failure locations as well as on the system's error correction need.

Abstract: Pre-charge voltage generation circuit for a random memory and a random memory are provided. The pre-charge voltage generation circuit is configured to selectively provide a pre-charge voltage and includes: a voltage generation module, configured to generate a first voltage and a second voltage, wherein either of the first voltage and the second voltage serves as the pre-charge voltage, the first voltage is greater than the second voltage; a selection module, coupled to the voltage generation module, configured to select and output the second voltage as the common end voltage of the storage capacitor of the random memory in response to an operation command being a write command, and configured to select and output the first voltage as the common end voltage in response to the operation command being a read command.

Abstract: A non-volatile memory, including n dies, where n is an integer greater than 1; at least one die of the n dies respectively receives a CRC operation execution instruction, and determines data to be verified of the at least one die according to the CRC operation execution instruction; for any die of the n dies, the die calculates a CRC code according to the data to be verified of the at least one die, to verify data to be verified of the non-volatile memory.

Abstract: A squelch detector is disclosed by the present application. By configuring the first to third bias current sources and a mirror ratio of the current mirror circuit, when an amplitude difference between first and second input signals is smaller or greater than a squelch threshold, flip of an output node in the squelch detector depends only on the squelch threshold and is independent of variations of process, voltage and temperature (PVT) parameters. Thus, the squelch detector can always provide reliable amplitude detection of input signals despite of possible variations of the PVT parameters.

Abstract: The present invention provides a memory controller and an MCU chip, in which a mirrored buffer with a small capacity built in the MCU can be time-division multiplexed as required by actual boot settings so that contents in the NVM are copied into the mirrored buffer at different times. Moreover, a CPU can read and run the copied contents in the mirrored buffer. Additionally, new contents are copied into the mirrored buffer during or after the CPU's execution of previously copied contents in such a manner that the newly copied contents can override part or the entirety of the previous contents. With this arrangement, hardware overhead can be reduced and significant reductions in MCU chip cost can be achieved, after each POR or system reset of the MCU chip, reduced contents are copied into the mirrored buffer, compared with the prior art, significantly shortening the startup time of the system.