Abstract: Delay locked loop (DLL) circuitry system and a memory device are disclosed. The DLL circuitry system includes a timer unit and a DLL circuit coupled thereto. The timer unit is enabled to generate a DLL enable signal based on the signal instructing the entry into a low power consumption mode and a predefined timer condition. The DLL enable signal enables the DLL circuit to realign an internal clock signal with an external clock signal. In this way, the DLL circuit is avoided from being unable to align the internal clock signal with the external clock signal because the memory device enters the low power mode which causes the variation of the power supply voltage of the DLL circuit. Moreover, a read or write error that may occur when data is to be read or written immediately after exiting the low power consumption mode is also avoided.

Abstract: Delay locked loop (DLL) circuitry system and a memory device are disclosed. The DLL circuitry system includes a timer unit and a DLL circuit coupled thereto. The timer unit is enabled to generate a DLL enable signal based on the signal instructing the entry into a low power consumption mode and a predefined timer condition. The DLL enable signal enables the DLL circuit to realign an internal clock signal with an external clock signal. In this way, the DLL circuit is avoided from being unable to align the internal clock signal with the external clock signal because the memory device enters the low power mode which causes the variation of the power supply voltage of the DLL circuit. Moreover, a read or write error that may occur when data is to be read or written immediately after exiting the low power consumption mode is also avoided.

Abstract: An X16 nonvolatile memory has 16 input/output (I/O) ports, identified as I/O ports [15:0], and adopts a conversion method, which allows the memory to operate in an X16 mode or in an X8 mode. The method includes receiving a first user command that is sent by an upper computer and belongs to a user mode; determining a disabling command for a module path of the high-bit I/O ports [15:8] according to the first user command; and executing the disabling command and disabling the module path for controlling the high-bit I/O ports [15:8] of the memory so as to operate in an X8 mode.

Abstract: Provided are a mode conversion method and a mode conversion apparatus for a nonvolatile memory. The method includes: receiving a first user command that is sent by an upper computer and belongs to a user mode, where the first user command includes an invoking path disabling instruction; sending an enable signal according to the invoking path disabling instruction; and disabling the module path for controlling the high-bit I/O ports [15:8] in the X16 nonvolatile memory according to the enable signal. After the module path for controlling the high-bit I/O ports [15:8] in the nonvolatile memory is disabled, data transmission and reception of the nonvolatile memory are implemented through the low-bit I/O ports [7:0], and the X16 nonvolatile memory is converted into an X8 mode.

Abstract: Disclosed are a nonvolatile memory and a programming method to reduce the tunnel oxide stress. The programming method includes: applying one program voltage pulse to a word line connected to a target memory cell, and then applying one or more incremental step voltage pulses to the word line connected to the target memory cell. The one program voltage pulse linearly increases from a first voltage level to a second voltage level, or the one program voltage pulse is in a staircase shape. The one or more incremental step voltage pulses start from an initial voltage level and have a predetermined step size.

Abstract: A nonvolatile memory includes: a memory cell array having a first portion and a second portion, a temperature sensor configured to measure a temperature of the memory cell array, and a controller. The first portion is programmable, readable and erasable to a predefined user, and the second portion is not programmable and erasable to the predefined user. The controller is configured to: perform an operation in the first portion in response to an instruction of the purchaser, and in response to determining that a predetermined condition is satisfied, write the temperature of the memory cell array when doing the operation and operation information related to the operation into the second portion.

Abstract: A NAND flash memory including a control unit which includes a signal receiving circuit and a flash array; the signal receiving circuit is used to receive a cache read command from an external NAND controller; the flash array includes at least one chip, each chip includes at least one plane, each plane includes a plurality of blocks, each block includes a plurality of pages; when a cache read command is received, it reads pages in a first block according to an address of the page until reaching the last page in the first block; when the last page in the first block is reached, an address of a next to-be-read page is generated according to an address of the last page in the first block to allow the cache read command to read the next to-be-read page.

Abstract: Provided are a programming method, programming apparatus and storage medium to reduce threshold voltage distribution in a non-volatile memory. The method includes performing program loops on a target page by sequentially using first programming voltages Vn; and when a predetermined condition is reached, proceeding to perform program loops on the target page by sequentially using second programming voltages Um until the target page is successfully programmed. Vn=V1+(n?1)×d1, where n denotes a program loop count of the first programming voltages, n is an integer greater than or equal to 1, and V1 and d1 are all positive numbers. Um=Vn+(m?1)×d2, where m denotes a program loop count of the second programming voltages, m is an integer greater than or equal to 2, and d2 is a positive number not equal to d1.

Abstract: The present application provides a NAND flash memory with wordline voltage compensate, including wordlines. Each wordline corresponds to a wordline voltage with a compensated temperature coefficient. The wordlines are divided into a plurality of groups, each group corresponds to a compensated temperature coefficient. Each wordline corresponds to a wordline address, and the groups of wordlines are divided by at least a border according to wordline addresses, or divided by zones having fixed number of wordlines.

Abstract: Methods, systems, and machine-readable storage medium for programming a storage device are disclosed. In some embodiments, the methods include: performing a verify operation on a plurality of storage elements of the storage device to determine whether the plurality of storage elements have been programmed to a first program state; determining a first number of failing bits corresponding to the first program state based on the verify operation; comparing the first number of failing bits with a first threshold of failing bits corresponding to the first program state; and determining a second threshold of failing bits based at least in part on the first number of failing bits and the comparison, wherein the second threshold of failing bits corresponds to a second program state.

Abstract: The present application provides a status output method in NAND flash memory, including, setting ALE signal, CLE signal and WE#, signal wherein ALE and/or CLE signal is set to be 1 and WE# signal is set to be 1; when a falling edge of the RE# is detected, outputting LUN status signal of the NAND flash memory. Further, there is provided a NAND flash memory, including I/O signal pins, which includes an ALE signal pin, an CLE signal pin, a WE# signal pin, and a RE# signal pin; wherein when the ALE signal output by the ALE pin and/or CLE signal output by the CLE pin is 1, and WE# signal output by the WE# pin is 1, once a falling edge of the RE# is detected, the LUN status signal of the NAND flash memory is detected.