Abstract: A memory, a method controlling method and a system are disclosed. The memory includes: an array of memory cells; a power manager; an instruction decoder; a controller; and an I/O interface, including a chip select pin. In the standby state, the instruction decoder and controller are enabled; in the power-down state, the instruction decoder is enabled; and in the deep power-down state, they are all disabled. In response to receiving a chip select signal, the memory enters the power-down state from the deep power-down state. The memory of the present disclosure provides the deep power-down state that disables the decoder, and the memory in the deep power-down state exits directly to the power-down state to achieve some functions without enabling all components, thereby reducing power consumption.

Abstract: An X16 nonvolatile memory has 16 input/output (I/O) ports, identified as I/O ports [15:0], and adopts a conversion method, which allows the memory to operate in an X16 mode or in an X8 mode. The method includes receiving a first user command that is sent by an upper computer and belongs to a user mode; determining a disabling command for a module path of the high-bit I/O ports [15:8] according to the first user command; and executing the disabling command and disabling the module path for controlling the high-bit I/O ports [15:8] of the memory so as to operate in an X8 mode.

Abstract: Provided are a mode conversion method and a mode conversion apparatus for a nonvolatile memory. The method includes: receiving a first user command that is sent by an upper computer and belongs to a user mode, where the first user command includes an invoking path disabling instruction; sending an enable signal according to the invoking path disabling instruction; and disabling the module path for controlling the high-bit I/O ports [15:8] in the X16 nonvolatile memory according to the enable signal. After the module path for controlling the high-bit I/O ports [15:8] in the nonvolatile memory is disabled, data transmission and reception of the nonvolatile memory are implemented through the low-bit I/O ports [7:0], and the X16 nonvolatile memory is converted into an X8 mode.