Abstract: A method and an apparatus for reading cache data, and a storage medium are provided. The method includes: receiving a read instruction; converting at least one type of address offset position corresponding to the read instruction into a coupled address offset position according to a preset rule; performing a matching operation in a data group according to the coupled address offset position which corresponds to the at least one type of address offset position and obtaining corresponding cache data; reading the cache data obtained through matching. This method is able to simultaneously perform matching operations and reading operations for at least two combined address offset positions, thereby greatly improving data reading efficiency and doubling cache data reading throughput without significantly increasing hardware logic. Furthermore, this configuration is applicable to read-only cache, read-write cache, and write-only cache, possessing great versatility.

Abstract: The present disclosure relates to a multi-view image generation apparatus and method, and a graphics processing unit. Waves are constructed according to primitive information and vertex information of geometric primitives to generate a plurality of waves for parallel processing, and the waves are scheduled by a wave management unit for execution, which can improve execution efficiency. Since the primitive information of the geometric primitives is stored in a first cache unit, data sharing between waves can be implemented. During the parallel processing of the waves, vertex information in a second cache unit is updated in real time according to vertex address information outputted by the waves, so that a raster processing unit can read the latest vertex information from the second cache unit. Finally, through an image generation unit, a multi-view image is generated according to image colors obtained by executions of the waves and views corresponding to pixel points.

Abstract: The present application relates to a graphics processing unit (GPU) performance analysis method and a computer device, and a storage medium. The method includes: submitting a GPU task queue generated by a central processing unit (CPU) to a GPU; the GPU task queue including a plurality of GPU tasks sorted by processing start moments, each of the GPU tasks being configured with respective access addresses of a plurality of storage spaces required to be accessed when the GPU task is processed; processing the plurality of GPU tasks through the GPU according to a processing time sequence of each GPU task in the task queue; and acquiring, for a memory access procedure required in a GPU task processing procedure, execution performance reference information of the GPU and/or the CPU for each GPU task according to access time information generated by the CPU and the GPU for the memory access procedure.

Abstract: The present disclosure relates to a grayscale compensation data generation method and apparatus, a device, a storage medium, and a program product. The method includes: acquiring brightness data of a plurality of grayscale images captured under a target shooting brightness, different grayscale images corresponding to different display grayscales; determining original grayscale compensation data of pixels corresponding to different display grayscales respectively according to the brightness data of the plurality of grayscale images; determining storage grayscales from a plurality of display grayscales; converting original grayscale compensation data of pixels corresponding to different storage grayscales respectively into target grayscale compensation data of block regions corresponding to the different storage grayscales, the block regions being regions including a plurality of pixels; and storing the target grayscale compensation data of the block regions corresponding to the different storage grayscales.

Abstract: Disclosed is a method and a device for decompressing Demura compensation value based on random-access bit stream. The method includes reading a target compression code corresponding to a target pixel set according to a screen refresh instruction in response to the screen refresh instruction, and decoding the target compression code to obtain Demura compensation values.

Abstract: Disclosed are a primitive rendering method and apparatus, a computer device, and a storage medium. The method includes: receiving primitive information, determining a target tile in which a primitive is located according to the primitive information, obtaining tile-based information corresponding to the primitive; buffering the primitive information and the tile-based information; when a preset condition is satisfied, rendering a primitive in each target tile according to the primitive information and the tile-based information. With the present disclosure, there is no need to frequently exchange the color information with the system memory, and this is also no need to exchange the primitive tile-based information with the system memory, thereby effectively reducing the data interaction between the on-chip data of the GPU and the system memory.

Abstract: The present disclosure relates to the computer technology and provides a method and a device for selecting a cache line to be replaced, and a storage medium. In the present disclosure, a blocking state binary tree is added to replace a replacement state binary tree, and a cache line to be replaced is selected based on the blocking state binary tree and a usage state binary tree, such that the earliest cache line, acting as the cache line to be replaced, can be accurately selected from the replaceable cache lines in a blocking cache.

Abstract: Programmable pixel blending method and apparatus, computer device, storage medium and computer program product are provided. The method includes: performing rasterization on a first triangle, a second triangle, and a third triangle via the raster unit to obtain triangle coverage information of each triangle; sending the triangle coverage information to the warp assembly unit and the warp reorder unit respectively; assembling, by the warp assembly unit, the first triangle and the second triangle into a first warp, and requesting a warp from a warp request interface based on information of the first warp; executing the first warp based on a warp information cache, a warp synchronization unit, the warp reorder unit, the pixel operation unit, the interpolation unit, and the execution unit; after the first warp is executed, continuing to assemble, by the warp assembly unit, the third triangle and completing a rendering of the third triangle.

Abstract: The present disclosure relates to a method for detecting a region of interest in an image, a video encoding method, apparatuses, a computer device, a storage medium, and a computer program product. The method includes: obtaining a current to-be-detected image frame, determining a mapping block size parameter value from encoding parameters corresponding to the current to-be-detected image frame, dividing the current to-be-detected image frame to obtain multiple mapping blocks based on the mapping block size parameter value, performing a texture region detection on each mapping block to obtain a texture region of interest detection result. performing a motion region of interest detection on each mapping block to obtain a motion region of interest detection result, and determining a region of interest of the current to-be-detected image frame based on the texture region of interest detection result and the motion region of interest detection result.

Abstract: Disclosed are parallel encoding and decoding method and apparatus, a computer device, a storage medium, and a computer program product. The method includes: acquiring a synchronization node corresponding to a codec core, and transmitting a frame synchronization detection request to the synchronization node based on a frame to be encoded and decoded; acquiring a frame synchronization result corresponding to the frame synchronization detection request; and determining a encoding and decoding mode for the frame to be encoded and decoded based on the frame synchronization result, and encoding and decoding the frame to be encoded and decoded based on the encoding and decoding mode. By using the method, a plurality of codec cores can be employed to code and decode different frames in the same video in parallel, thereby improving the frame rate.

Abstract: A pixel circuit includes a drive transistor, a data writing module, a storage module, and a light emitting control module; a first terminal of the storage module is configured to receive a first power supply voltage signal, and a second terminal of the storage module is configured to be connected to a control electrode of the drive transistor; a first terminal of the data writing module is configured to receive a data signal, and a second terminal of the data writing module is configured to be connected to the control electrode of the drive transistor; a substrate of the drive transistor is configured to receive a second voltage signal, a first electrode of the drive transistor is configured to receive the first power supply voltage signal, and a second electrode of the drive transistor is configured to be connected to at least partial light emitting control module.

Abstract: Disclosed are a thread construction method and device. The method includes: a workload is divided into a plurality of work groups; for any work group, a pattern type that matches a size of the any work group is selected, a target thread construction pattern is determined from a plurality of candidate thread construction patterns corresponding to the pattern type; a plurality of threads are constructed according to the target thread construction pattern; the threads are composed of a plurality of consecutive work items in the any work group; the work item index corresponding to at least one key work item in the work item sequence of each thread is cached and the work item index of each thread is obtained, which is configured to schedule the any work item corresponding to the thread to the processing unit.

Abstract: The disclosure relates to a luma adjustment method and apparatus, a computer device, a storage medium, and a computer program product. The method includes: acquiring a first luma requirement or a second luma requirement; acquiring, based on a current image of a display page, a luma map corresponding to the current image; converting the luma map from a linear space to a logarithmic space when the luma adjustment requirement is the first luma requirement; filtering the luma map to acquire a base layer image and a detail layer image; compressing the base layer image and the detail layer image based on a configuration parameter for merging, to obtain a merged image; converting the merged image from the logarithmic space to the linear space when the luma adjustment requirement is the first luma requirement; and adjusting luma of the display page based on the luma map and the merged image.

Abstract: Disclosed are a data loading method and apparatus for a convolution operation, a computer device, a storage medium and a computer program product. The method includes: splitting a feature image to be loaded into the cache unit into a plurality of sub-feature images; determining a target cache line corresponding to each of the sub-feature images in each of the cache lines according to a positional relationship of each of the sub-feature images in the feature image; wherein target cache lines corresponding to at least two sub-feature images with the same positional relationship are located in the same cache set, and target cache lines corresponding to at least two sub-feature images with an adjacent positional relationship are located in different cache sets; loading a data content of each of the sub-feature images into the target cache line corresponding to each of the sub-feature images.

Abstract: The present disclosure relates to a conditional branch coverage calculation method and device, computer apparatus, storage medium and computer program product. The method includes: acquiring code types of uncovered conditional branch code lines in target code, and acquiring comment information corresponding to the uncovered conditional branch code lines according to the code type; acquiring coverage parameter corresponding to the uncovered conditional branch code lines according to the comment information corresponding to the uncovered conditional branch code lines; and calculating a conditional branch coverage corresponding to the target code according to the coverage parameters corresponding to the uncovered conditional branch code lines and a total number of conditional branch code lines in the target code.

Abstract: A method for compressing Demura compensation value including: acquiring original compensation values of a target panel; inputting the original compensation values into a spatial domain sampling model, performing a down-sampling to obtain spatial domain sampling values, inputting the original compensation values into a prediction mode overall model, and performing a numerical processing to obtain a plurality of mode characteristic values; performing a data reconstruction on the spatial sampling values and the plurality of mode characteristic values to obtain a reconstructed value set; performing a syntactic encoding on the spatial sampling values and the plurality of mode characteristic values to obtain a syntactic element code set; performing a mode selection according to the reconstructed value set and the syntactic element code set to obtain an optimal prediction mode; and acquiring and outputting a syntactic element code corresponding to the optimal prediction mode to obtain a Demura compensation value com

Abstract: The present disclosure relates to an image scaling method and an apparatus thereof. The method includes: for at least one interpolation pixel in a source image, grouping at least two adjacent pixels of the interpolation pixel to obtain adjacent pixel sets; no intersection existing between the adjacent pixel sets; determining, based on position relationships between the interpolation pixel and regions formed by the adjacent pixel sets, virtual interpolation pixels corresponding to the interpolation pixel in the regions formed by the adjacent pixel sets respectively; calculating corresponding pixel sampling values of the virtual interpolation pixels in the source image according to a preset bilinear interpolation algorithm respectively; and generating theoretical pixel values corresponding to the interpolation pixel based on the pixel sampling values corresponding to the virtual interpolation pixels; the theoretical pixel values being configured to perform image scaling on the source image.

Abstract: An image display method includes: obtaining attribute information of each of sub-pixels in an under-display camera region and in a normal display region; calculating a compensated brightness value of the under-display camera region and an attenuated brightness value of the normal display region according to the attribute information; displaying an image according to the compensated brightness value of the under-display camera region and the attenuated brightness value of the normal display region.

Abstract: The present disclosure relates to a data process apparatus and a method thereof. The data process apparatus includes an internal memory unit and a shader level-1 cache. The internal memory unit is configured to store a to-be-cached matrix. The to-be-cached matrix includes at least a first element and a second element. The first element and the second element are stored in the internal memory unit in order of elements. The first element is located in a first row of the to-be-cached matrix, and the second element is located in next row of the to-be-cached matrix adjacent to the first row. The shader level-1 cache is connected to the internal memory unit, and configured to acquire the to-be-cached matrix to obtain a to-be-processed matrix stored in order of elements, and store the to-be-processed matrix.

Abstract: An electronic apparatus and a method for reducing the number of commands are provided. The electronic apparatus includes a central processor and a co-processor. The central processor generates a plurality of original register setting commands to set at least one bit of at least one register of the co-processor. The original register setting commands include a plurality of first original register setting commands, and a plurality of setting targets of the first original register setting commands have address continuity. The central processor merges the first original register setting commands to generate at least one merged register setting command. The central processor transmits the at least one merged register setting command to the co-processor.