Abstract: An image display method includes: obtaining attribute information of each of sub-pixels in an under-display camera region and in a normal display region; calculating a compensated brightness value of the under-display camera region and an attenuated brightness value of the normal display region according to the attribute information; displaying an image according to the compensated brightness value of the under-display camera region and the attenuated brightness value of the normal display region.

Abstract: The present disclosure relates to a data process apparatus and a method thereof. The data process apparatus includes an internal memory unit and a shader level-1 cache. The internal memory unit is configured to store a to-be-cached matrix. The to-be-cached matrix includes at least a first element and a second element. The first element and the second element are stored in the internal memory unit in order of elements. The first element is located in a first row of the to-be-cached matrix, and the second element is located in next row of the to-be-cached matrix adjacent to the first row. The shader level-1 cache is connected to the internal memory unit, and configured to acquire the to-be-cached matrix to obtain a to-be-processed matrix stored in order of elements, and store the to-be-processed matrix.

Abstract: An electronic apparatus and a method for reducing the number of commands are provided. The electronic apparatus includes a central processor and a co-processor. The central processor generates a plurality of original register setting commands to set at least one bit of at least one register of the co-processor. The original register setting commands include a plurality of first original register setting commands, and a plurality of setting targets of the first original register setting commands have address continuity. The central processor merges the first original register setting commands to generate at least one merged register setting command. The central processor transmits the at least one merged register setting command to the co-processor.

Abstract: An electronic apparatus and a method for reducing the number of commands are provided. The electronic apparatus includes a central processor and a co-processor. The central processor generates a plurality of original register setting commands to set at least one bit of at least one register of the co-processor. The original register setting commands include a plurality of first original register setting commands, and a plurality of setting targets of the first original register setting commands have address continuity. The central processor merges the first original register setting commands to generate at least one merged register setting command. The central processor transmits the at least one merged register setting command to the co-processor.

Abstract: A computation method used in a convolutional neural network is provided. The method includes: receiving original data; determining a first optimal quantization step size according to a distribution of the original data; performing fixed-point processing to the original data according to the first optimal quantization step size to generate first data; inputting the first data to a first layer of the convolutional neural network to generate first output data; determining a second optimal quantization step size according to a distribution of the first output data; performing the fixed-point processing to the first output data according to the second optimal quantization step size to generate second data; and inputting the second data to a second layer of the convolutional neural network.

Abstract: A graphics processing unit includes a pixel shader, an output merger, a cache, and a memory. The pixel shader is configured to output a pixel data. The output merger is coupled to the pixel shader and configured to receive the pixel data. The output merger outputs the pixel data and a sample mask corresponding to the pixel data. The cache is coupled to the output merger and configured to receive the pixel data and the sample mask. The cache generates a sample data according to the pixel data and the sample mask. The memory is coupled to the cache. The cache writes the sample data into the memory. A data size of the sample data is a multiple of a data size of the pixel data. An operation method thereof is also provided.

Abstract: An electronic apparatus and a method for reducing the number of commands are provided. The electronic apparatus includes a central processor and a co-processor. The central processor generates a plurality of original register setting commands to set at least one bit of at least one register of the co-processor. The original register setting commands include a plurality of first original register setting commands, and a plurality of setting targets of the first original register setting commands have address continuity. The central processor merges the first original register setting commands to generate at least one merged register setting command. The central processor transmits the at least one merged register setting command to the co-processor.

Abstract: Disclosed are a pixel driving circuit and method, and a display device. The pixel driving circuit includes: the first port of the operation module is electrically connected via the first switch unit to the compensation wire connected to the pixel driving module, the second port of the operation module is electrically connected to the compensation wire through the second switch unit; the first switch unit is configured to transmit the driving data provided by the pixel driving module to the operation module in the self-discharge phase, and the operation module is configured to perform the calculation on the driving data in the self-discharge phase to obtain compensation data; the second switch unit is configured to write the compensation data into the pixel driving module through the compensation wire in the data writing stage.

Abstract: A graphics processing unit includes a pixel shader, an output merger, a cache, and a memory. The pixel shader is configured to output a pixel data. The output merger is coupled to the pixel shader and configured to receive the pixel data. The output merger outputs the pixel data and a sample mask corresponding to the pixel data. The cache is coupled to the output merger and configured to receive the pixel data and the sample mask. The cache generates a sample data according to the pixel data and the sample mask. The memory is coupled to the cache. The cache writes the sample data into the memory. A data size of the sample data is a multiple of a data size of the pixel data. An operation method thereof is also provided.

Abstract: A method for displaying graphic layers is provided. The method includes: receiving a plurality of graphic layers; assigning sequence numbers to the graphic layers according to an overlay order; and displaying the graphic layers in a sequence order according to the sequence numbers.