Abstract: In an exemplary embodiment, a method of fabricating an integrated circuit includes designing an optical photomask for forming a pre-pattern opening in a photoresist layer on a semiconductor substrate, wherein the photoresist layer and the pre-pattern opening are coated with a self-assembly material that undergoes directed self-assembly (DSA) to form a DSA pattern. The step of designing the optical photomask includes using a computing system, inputting a DSA target pattern, and using the computing system, applying a DSA model to the DSA target pattern to generate a first DSA directing pattern. Further, the step of designing the optical photomask includes using the computing system, calculating a residual between the DSA target pattern and the DSA directing pattern, and using the computing system, applying the DSA model to the first DSA directing pattern and the residual to generate a second, updated DSA directing pattern.

Abstract: A method of fabricating an integrated circuit includes designing an optical photomask for forming a pre-pattern opening in a photoresist layer on a semiconductor substrate, wherein the photoresist layer and the pre-pattern opening are coated with a self-assembly material that undergoes directed self-assembly (DSA) to form a DSA pattern. Designing the optical photomask includes using a computing system, inputting a DSA target pattern, and using the computing system, applying a DSA model to the DSA target pattern to generate a first DSA directing pattern. Further, the step of designing the optical photomask includes using the computing system, calculating a residual between the DSA target pattern and the DSA directing pattern, and using the computing system, applying the DSA model to the first DSA directing pattern and the residual to generate a second, updated DSA directing pattern. Generating the second, updated DSA directing pattern includes linearizing a self-consistent field theory equation.

Abstract: This application is directed to a semiconductor device with an oversized local contact as a Faraday shield, and methods of making such a semiconductor device. One illustrative device disclosed herein includes a transistor comprising a gate electrode and a source region, a source region conductor that is conductively coupled to the source region, a Faraday shield positioned above the source region conductor and the gate electrode and a first portion of a first primary metallization layer for an integrated circuit device positioned above and electrically coupled to the Faraday shield.

Abstract: When forming high-k metal gate electrode structures in transistors of different conductivity type while also incorporating an embedded strain-inducing semiconductor alloy selectively in one type of transistor, superior process uniformity may be accomplished by selectively reducing the thickness of a dielectric cap material of a gate layer stack above the active region of transistors which do not receive the strain-inducing semiconductor alloy. In this case, superior confinement and thus integrity of sensitive gate materials may be accomplished in process strategies in which the sophisticated high-k metal gate electrode structures are formed in an early manufacturing stage, while, in a replacement gate approach, superior process uniformity is achieved upon exposing the surface of a placeholder electrode material.

Abstract: The drain and source regions may at least be partially formed by in situ doped epitaxially grown semiconductor materials for complementary transistors in sophisticated semiconductor devices designed for low power and high performance applications. To this end, cavities may be refilled with in situ doped semiconductor material, which in some illustrative embodiments also provides a desired strain in the channel regions of the complementary transistors.

Abstract: The width of scribe lines may be reduced in semiconductor devices by applying a process technique in which trenches may be formed first from the rear side on the basis of a required width of the corresponding trenches, while subsequently it may be cut into the substrate from the front side on the basis of a reduced thickness of the corresponding saw blades, thereby also enabling a reduction of the scribe line width. Furthermore, contamination of the front side, i.e., of the metallization system, may be reduced, for instance, by performing an optional intermediate cleaning process.

Abstract: A hardmask layer is formed with an increased etch resistance based on alternating nanolayers of TiN with alternating residual stresses. Embodiments include depositing a first nanolayer of TiN, and depositing a second nanolayer of TiN on the first nanolayer, wherein the first and second nanolayers have different residual stresses.

Abstract: An approach is provided for applying post graphic data system (GDS) stream enhancements back to the design stage. Embodiments include receiving a data stream of an integrated circuit design layout from a design stage, determining one or more design constructs based on an analysis of the data stream, determining one or more instructions to implement the one or more design constructs at the design stage, and sending the instructions to the design stage to implement the one or more design constructs.

Abstract: Semiconductor devices and methods of forming semiconductor devices are provided herein. In an embodiment, a semiconductor device includes a semiconductor substrate. A source region and a drain region are disposed in the semiconductor substrate. A channel region is defined in the semiconductor substrate between the source region and the drain region. A gate dielectric layer overlies the channel region of the semiconductor substrate, and a gate electrode overlies the gate dielectric layer. The channel region includes a first carbon-containing layer, a doped layer overlying the first carbon-containing layer, a second carbon-containing layer overlying the doped layer, and an intrinsic semiconductor layer overlying the second carbon-containing layer. The doped layer includes a dopant that is different than carbon.

Abstract: Disclosed herein are various methods of forming a layer of silicon on a layer of silicon/germanium. In one example, a method disclosed herein includes forming a silicon/germanium material on a semiconducting substrate, after forming the silicon/germanium material, performing a heating process to raise a temperature of the substrate to a desired silicon formation temperature while flowing a silicon-containing precursor and a chlorine-containing precursor into the deposition chamber during the heating process, and, after the temperature of the substrate reaches the desired silicon formation temperature, forming a layer of silicon on the silicon/germanium material.

Abstract: Methods and structures are described for determining contact resistivities and Schottky barrier heights for conductors deposited on semiconductor wafers that can be combined with combinatorial processing, allowing thereby numerous processing conditions and materials to be tested concurrently. Methods for using multi-ring as well as single-ring CTLM structures to cancel parasitic resistance are also described, as well as structures and processes for inline monitoring of properties.

Abstract: A capping layer is formed over a hardmask layer to increase the etch resistance and overall performance of the hardmask layer. Embodiments include forming a hardmask layer over a substrate and forming a capping layer on the hardmask layer, the capping layer including a stack of at least two nanolayers.

Abstract: One illustrative device disclosed herein includes a plurality of fins separated by a trench formed in a semiconducting substrate, a first layer of insulating material positioned in the trench, the first layer of insulating material having an upper surface that is below an upper surface of the substrate, an isolation layer positioned within the trench above the first layer of insulating material, the isolation layer having an upper surface that is below the upper surface of the substrate, a second layer of insulating material positioned within the trench above the isolation layer, the second layer of insulating material having an upper surface that is below the upper surface of the substrate, and a gate structure positioned above the second layer of insulating material.

Abstract: Disclosed herein are various methods of forming a metal cap layer on copper-based conductive structures on integrated circuit devices, and integrated circuit devices having such a structure. In one example, the method includes the steps of forming a conductive feature comprised of copper in a layer of insulating material, performing a metal removal process to remove a portion of the conductive feature and thereby define a recess above a residual portion of the copper feature, and performing a selective deposition process to form a cap layer comprised of cobalt, manganese, CoWP or NiWP within the recess.

Abstract: A process monitoring system may detect out-of-control situations on the basis of a single criterion for a plurality of different lithography processes. To this end, each data set related to a specific type of lithography process may be processed so as to determine relative data, which may be centered around the same mean value for each of the different process types for a standard control situation.

Abstract: A method for fabricating an integrated circuit is disclosed that includes, in accordance with an embodiment, providing an integrated circuit comprising a p-type field effect transistor (pFET), recessing a surface region of the pFET using an ammonia-hydrogen peroxide-water (APM) solution to form a recessed pFET surface region, and depositing a silicon-based material channel on the recessed pFET surface region.

Abstract: In sophisticated semiconductor devices comprising high-k metal gate electrode structures formed on the basis of a replacement gate approach, semiconductor-based resistors may be provided without contributing to undue process complexity in that the resistor region is recessed prior to depositing the semiconductor material of the gate electrode structure. Due to the difference in height level, a reliable protective dielectric material layer is preserved above the resistor structure upon exposing the semiconductor material of the gate electrode structure and removing the same on the basis of selective etch recipes. Consequently, well-established semiconductor materials, such as polysilicon, may be used for the resistive structures in complex semiconductor devices, substantially without affecting the overall process sequence for forming the sophisticated replacement gate electrode structures.

Abstract: Generally, the present disclosure is directed to techniques for improving the reliability of semiconductor devices with high-k gate dielectric layers by passivating point defects during the gate stack formation. One illustrative method disclosed herein includes performing a plurality of material deposition cycles to form a high-k dielectric layer above a semiconductor material layer, and introducing a passivating material into a gaseous precursor that is used for forming the high-k dielectric layer during at least one of the plurality of material deposition cycles.

Abstract: A process is provided for selective removal of one or more unwanted fins during FINFET device fabrication. In one aspect, the process includes: providing a conformal protective layer over multiple fin structures on a substrate; patterning one or more openings over the unwanted fin structure(s); and removing at least a top portion of the unwanted fin structure(s) exposed through the opening(s), the removing including removing at least a portion of the conformal protective layer over the unwanted fin structure(s) exposed through the opening(s). In enhanced aspects, the removing includes removing a hard mask from the at least one unwanted fin structure(s) exposed through the opening(s), and selectively removing semiconductor material of at least one unwanted fin structure(s). The conformal protective layer protects one or more remaining fin structures during the selective removal of the semiconductor material of the unwanted fin structure(s).

Abstract: Contact elements of sophisticated semiconductor devices may be formed for gate electrode structures and for drain and source regions in separate process sequences in order to apply electroless plating techniques without causing undue overfill of one type of contact opening. Consequently, superior process uniformity in combination with a reduced overall contact resistance may be accomplished. In some illustrative embodiments, cobalt may be used as a contact metal without any additional conductive barrier materials.