Patents Assigned to GLOBALFOUNDRIES Inc.
  • FABRICATION OF SILICON OXIDE AND OXYNITRIDE HAVING SUB-NANOMETER THICKNESS
    Publication number: 20120329230
    Abstract: A method of fabricating a silicon-containing oxide layer that includes providing a chemical oxide layer on a surface of a semiconductor substrate, removing the chemical oxide layer in an oxygen-free environment at a temperature of 1000° C. or greater to provide a bare surface of the semiconductor substrate, and introducing an oxygen-containing gas at a flow rate to the bare surface of the semiconductor substrate for a first time period at the temperature of 1000° C. The temperature is then reduced to room temperature during a second time period while maintaining the flow rate of the oxygen containing gas to provide a silicon-containing oxide layer having a thickness ranging from 0.5 ? to 10 ?.
    Type: Application
    Filed: June 21, 2011
    Publication date: December 27, 2012
    Applicants: GLOBALFOUNDRIES INC., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael P. Chudzik, Min Dai, Joseph F. Shepard, JR., Shahab Siddiqui, Jinping Liu
  • METHODS OF FABRICATING A SEMICONDUCTOR IC HAVING A HARDENED SHALLOW TRENCH ISOLATION (STI)
    Publication number: 20120329239
    Abstract: Methods and provided for fabricating a semiconductor IC having a hardened shallow trench isolation (STI). In accordance with one embodiment the method includes providing a semiconductor substrate and forming an etch mask having an opening exposing a portion the semiconductor substrate. The exposed portion is etched to form a trench extending into the semiconductor substrate and an oxide is deposited to at least partially fill the trench. At least the surface portion of the oxide is plasma nitrided to form a nitrided oxide layer and then the etch mask is removed.
    Type: Application
    Filed: June 23, 2011
    Publication date: December 27, 2012
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Thorsten Kammler, Joerg Radecker, Christof Streck
  • Method of Improving Memory Cell Device by Ion Implantation
    Publication number: 20120329220
    Abstract: Disclosed herein is a method of forming a memory device. In one example, the method includes performing a first ion implantation process with dopant atoms of a first type to partially form extension implant regions for a pull-down transistor and to fully form extension implant regions for a pass gate transistor of the memory device and, after performing the first ion implantation process, forming a first masking layer that masks the pass gate transistor and exposes the pull-down transistor to further processing. The method concludes with the step of performing a second ion implantation process with dopant atoms of the first type to introduce additional dopant atoms into the extension implant regions for the pull-down transistor that were formed during the first ion implantation process while masking the pass gate transistor from the second ion implantation process with the first masking layer.
    Type: Application
    Filed: June 27, 2011
    Publication date: December 27, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Ralf van Bentum, Nihar-Ranjan Mohapatra
  • Stress engineering in a contact level of semiconductor devices by stressed conductive layers and an isolation spacer
    Patent number: 8338284
    Abstract: In sophisticated semiconductor devices, strain-inducing materials having a reduced dielectric strength or having certain conductivity, such as metal nitride and the like, may be used in the contact level in order to enhance performance of circuit elements, such as field effect transistors. For this purpose, a strain-inducing material may be efficiently encapsulated on the basis of a dielectric layer stack that may be patterned prior to forming the actual interlayer dielectric material in order to mask sidewall surface areas on the basis of spacer elements.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: December 25, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Kai Frohberg, Hartmut Ruelke, Volker Jaschke, Joerg Hohage, Frank Seliger
  • Forming semiconductor resistors in a semiconductor device comprising metal gates by increasing etch resistivity of the resistors
    Patent number: 8338306
    Abstract: In a replacement gate approach, the polysilicon material may be efficiently removed during a wet chemical etch process, while the semiconductor material in the resistive structures may be substantially preserved. For this purpose, a species such as xenon may be incorporated into the semiconductor material of the resistive structure, thereby imparting a significantly increased etch resistivity to the semiconductor material. The xenon may be incorporated at any appropriate manufacturing stage.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: December 25, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jens Heinrich, Ralf Richter, Katja Steffen, Johannes Groschopf, Frank Seliger, Andreas Ott, Manfred Heinz, Andy Wei
  • Transistor device comprising an embedded semiconductor alloy having an asymmetric configuration
    Patent number: 8338274
    Abstract: In sophisticated semiconductor devices, an asymmetric transistor configuration may be obtained on the basis of a strain-inducing semiconductor alloy. To this end, strain relaxation implantation processes may be performed at the drain side according to some illustrative embodiments, while, in other cases, the deposition of the strain-inducing alloy may be performed in an asymmetric manner with respect to the drain side and the source side of the transistor.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: December 25, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Vassilios Papageorgiou, Gunda Beernink, Jan Hoentschel
  • Strain enhancement in transistors comprising an embedded strain-inducing semiconductor alloy by corner rounding at the top of the gate electrode
    Patent number: 8338892
    Abstract: In MOS transistor elements, a strain-inducing semiconductor alloy may be embedded in the active region with a reduced offset from the channel region by applying a spacer structure of reduced width. In order to reduce the probability of creating semiconductor residues at the top area of the gate electrode structure, a certain degree of corner rounding of the semiconductor material may be introduced, which may be accomplished by ion implantation prior to epitaxially growing the strain-inducing semiconductor material. This concept may be advantageously combined with the provision of sophisticated high-k metal gate electrodes that are provided in an early manufacturing stage.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: December 25, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Roman Boschke, Maciej Wiatr, Peter Javorka
  • HIGH-K METAL GATE ELECTRODE STRUCTURES FORMED BY REDUCING A GATE FILL ASPECT RATIO IN REPLACEMENT GATE TECHNOLOGY
    Publication number: 20120319205
    Abstract: When forming sophisticated high-k metal gate electrode structures on the basis of a replacement gate approach, the fill conditions upon filling in the highly conductive electrode metal, such as aluminum, may be enhanced by removing an upper portion of the final work function metal, for instance a titanium nitride material in P-channel transistors. In some illustrative embodiments, the selective removal of the metal-containing electrode material in an upper portion of the gate opening may be accomplished without unduly increasing overall process complexity.
    Type: Application
    Filed: June 6, 2012
    Publication date: December 20, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Klaus Hempel, Andy Wei, Martin Mazur
  • Method of Forming Conductive Contacts on a Semiconductor Device with Embedded Memory and the Resulting Device
    Publication number: 20120322225
    Abstract: A method is disclosed that includes forming a conductive logic contact in a logic area of a semiconductor device, forming a bit line contact and a capacitor contact in a memory array of the semiconductor device, and performing at least one first common process to form a first metallization layer comprising a first conductive line in the logic area that is conductively coupled to the conductive logic contact and a bit line in the memory array that is conductively coupled to the bit line contact. The method further includes performing at least one second common process to form a second metallization layer comprising a first conductive structure conductively coupled to the first conductive line in the logic area and a second conductive structure in the memory array that that is conductively coupled to the capacitor contact.
    Type: Application
    Filed: June 20, 2011
    Publication date: December 20, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Till Schloesser, Peter Baars
  • INTEGRATED CIRCUITS INCLUDING BARRIER POLISH STOP LAYERS AND METHODS FOR THE MANUFACTURE THEREOF
    Publication number: 20120319285
    Abstract: Embodiments of a method for fabricating integrated circuits are provided, as are embodiments of an integrated circuit. In one embodiment, the method includes the steps of depositing an interlayer dielectric (“ILD”) layer over a semiconductor device, depositing a barrier polish stop layer over the ILD layer, and patterning at least the barrier polish stop layer and the ILD layer to create a plurality of etch features therein. Copper is plated over the barrier polish stop layer and into the plurality of etch features to produce a copper overburden overlying the barrier polish stop layer and a plurality of conductive interconnect features in the ILD layer and barrier polish stop layer. The integrated circuit is polished to remove the copper overburden and expose the barrier polish stop layer.
    Type: Application
    Filed: June 17, 2011
    Publication date: December 20, 2012
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Egon Ronny PFÜTZNER, Carsten PETERS, Jens HEINRICH
  • Methods for forming isolated fin structures on bulk semiconductor material
    Patent number: 8334177
    Abstract: Methods are provided for fabricating a semiconductor device. A method comprises forming a layer of a first semiconductor material overlying the bulk substrate and forming a layer of a second semiconductor material overlying the layer of the first semiconductor material. The method further comprises creating a fin pattern mask on the layer of the second semiconductor material and anisotropically etching the layer of the second semiconductor material and the layer of the first semiconductor material using the fin pattern mask as an etch mask. The anisotropic etching results in a fin formed from the second semiconductor material and an exposed region of first semiconductor material underlying the fin. The method further comprises forming an isolation layer in the exposed region of first semiconductor material underlying the fin.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: December 18, 2012
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Witold Maszara, Hemant Adhikari
  • Buried etch stop layer in trench isolation structures for superior surface planarity in densely packed semiconductor devices
    Patent number: 8334573
    Abstract: Material erosion of trench isolation structures in advanced semiconductor devices may be reduced by incorporating an appropriate mask layer stack in an early manufacturing stage. For example, a silicon nitride material may be incorporated as a buried etch stop layer prior to a sequence for patterning active regions and forming a strain-inducing semiconductor alloy therein, wherein, in particular, the corresponding cleaning process prior to the selective epitaxial growth process has been identified as a major source for causing deposition-related irregularities upon depositing the interlayer dielectric material.
    Type: Grant
    Filed: August 18, 2010
    Date of Patent: December 18, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Maciej Wiatr, Markus Forsberg, Stephan Kronholz, Roman Boschke
  • Early embedded silicon germanium with insitu boron doping and oxide/nitride proximity spacer
    Patent number: 8334185
    Abstract: Devices are formed with an oxide liner and nitride layer before forming eSiGe spacers. Embodiments include forming first and second gate stacks on a substrate, forming an oxide liner over the first and second gate stacks, forming a nitride layer over the oxide liner, forming a resist over the first gate stack, forming nitride spacers from the nitride layer over the second gate stack, forming eSiGe source/drain regions for the second gate stack, subsequently forming halo/extension regions for the first gate stack, and independently forming halo/extension regions for the second gate stack. Embodiments include forming the eSiGe regions by wet etching the substrate with TMAH using the nitride spacers as a soft mask, forming sigma shaped cavities, and epitaxially growing in situ boron doped eSiGe in the cavities.
    Type: Grant
    Filed: April 19, 2011
    Date of Patent: December 18, 2012
    Assignee: Globalfoundries Inc.
    Inventors: Stephan Kronholz, Matthias Kessler, Ricardo Mikalo
  • Flexible job preparation and control
    Patent number: 8335581
    Abstract: Preparation of a wafer processing or measuring tool for a job can be initiated prior to assigning a wafer carrier to deliver wafers to the tool. The automated process may include transfer of wafers from a container, such as a bare wafer stocker, or between two tools.
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: December 18, 2012
    Assignee: Globalfoundries Inc.
    Inventors: Raymond G. Goss, Diwas Adhikari
  • Methods for fabricating an electrically correct integrated circuit
    Patent number: 8336011
    Abstract: A method for fabricating an integrated circuit is disclosed that includes, in accordance with an embodiment, providing a logical design for the semiconductor device and comparing an element in the logical design to a library of element patterns. The library of element patterns is derived by identifying layout patterns having electrical properties that deviate from modeled properties; the library also includes a quantitative measure of deviation from the modeled properties. In response to the comparing and with consideration of the quantitative measure, a determination is made as to whether the element is acceptable in the logical design. A mask set is generated that implements the logical design using either the element or a modified element if the element is not acceptable, and the mask set is employed to implement the logical design in and on a semiconductor substrate.
    Type: Grant
    Filed: February 7, 2011
    Date of Patent: December 18, 2012
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventor: Rasit Topaloglu
  • Metal Gate Stack Formation for Replacement Gate Technology
    Publication number: 20120315749
    Abstract: Generally, the subject matter disclosed herein relates to modern sophisticated semiconductor devices and methods for forming the same, wherein a reduced threshold voltage (Vt) may be achieved in HK/MG transistor elements that are manufactured based on replacement gate electrode integrations. One illustrative method disclosed herein includes forming a first metal gate electrode material layer above a gate dielectric material layer having a dielectric constant of approximately 10 or greater. The method further includes exposing the first metal gate electrode material layer to an oxygen diffusion process, forming a second metal gate electrode material layer above the first metal gate electrode material layer, and adjusting an oxygen concentration gradient and a nitrogen concentration gradient in at least the first metal gate electrode material layer and the gate dielectric material layer.
    Type: Application
    Filed: June 7, 2011
    Publication date: December 13, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Klaus Hempel, Andy C. Wei, Robert Binder, Joachim Metzger
  • FIN-FET DEVICE AND METHOD AND INTEGRATED CIRCUITS USING SUCH
    Publication number: 20120313169
    Abstract: FIN-FET ICs with adjustable FIN-FET channel widths are formed from a semiconductor layer (42). Fins (36) may be etched from the layer (42) and then some (46) locally shortened or the layer (42) may be locally thinned and then fins (46) of different fin heights etched therefrom. Either way provides fins (46) and FIN-FETs (40) with different channel widths W on the same substrate (24). Fin heights (H) are preferably shortened by implanting selected ions (A, B, C, etc.) through a mask (90, 90?, 94, 94?, 97, 97?) to locally enhance the etch rate of the layer (42) or some of the fins (36). The implant(s) (A, B, C, etc.) is desirably annealed and then differentially etched. This thins part(s) (42-i) of the layer (42) from which the fins (46) are then etched or shortens some of the fins (46) already etched from the layer (42). For silicon, germanium is a suitable implant ion.
    Type: Application
    Filed: June 9, 2011
    Publication date: December 13, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Jeremy Wahl, Kingsuk Maitra
  • Buried Sublevel Metallizations for Improved Transistor Density
    Publication number: 20120313176
    Abstract: Generally, the subject matter disclosed herein relates to modern sophisticated semiconductor devices and methods for forming the same, wherein electrical interconnects between circuit elements based on a buried sublevel metallization may provide improved transistor density. One illustrative method disclosed herein includes forming a contact dielectric layer above first and second transistor elements of a semiconductor device, and after forming the contact dielectric layer, forming a buried conductive element below an upper surface of the contact dielectric layer, the conductive element providing an electrical connection between the first and second transistor elements.
    Type: Application
    Filed: June 7, 2011
    Publication date: December 13, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Kai Frohberg, Dominik Olligs, Jens Heinrich, Katrin Reiche
  • COPPER INTERCONNECT WITH METAL HARDMASK REMOVAL
    Publication number: 20120315755
    Abstract: A passivation layer is formed on inlaid Cu for protection against oxidation and removal during subsequent removal of an overlying metal hardmask. Embodiments include treating an exposed upper surface of inlaid Cu with hydrofluoric acid and a copper complexing agent, such as benzene triazole, to form a passivation monolayer of a copper complex, etching to remove the metal hardmask, removing the passivation layer by heating to at least 300° C., and forming a barrier layer on the exposed upper surface of the inlaid Cu.
    Type: Application
    Filed: June 10, 2011
    Publication date: December 13, 2012
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Christin Bartsch, Susanne Leppack
  • Method of Removing Gate Cap Materials While Protecting Active Area
    Publication number: 20120313187
    Abstract: Disclosed herein is a method of forming a semiconductor device. In one example, the method includes forming a gate electrode structure above a semiconducting substrate, wherein the gate electrode structure includes a gate insulation layer, a gate electrode, a first sidewall spacer positioned proximate the gate electrode, and a gate cap layer, and forming an etch stop layer above the gate cap layer and above the substrate proximate the gate electrode structure. The method further includes forming a layer of spacer material above the etch stop layer, and performing at least one first planarization process to remove the portion of said layer of spacer material positioned above the gate electrode, the portion of the etch stop layer positioned above the gate electrode and the gate cap layer.
    Type: Application
    Filed: June 7, 2011
    Publication date: December 13, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Peter Baars, Till Schloesser, Frank Jakubowski