Abstract: A circuit and method for generating cyclic redundancy check (CRC) data is disclosed. In one embodiment, the circuit interfaces with a data bus with other processor components. The circuit includes an input first-in-first-out (FIFO) to interface with the data bus, a configuration register electrically coupled to the data bus, and a configurable CRC generation circuit electrically coupled to the data bus and to the configuration register. The CRC generation circuit includes a bit shift register which is configurable to generate CRC data for multiple protocols. To accomplish this, the bit shift register is configurable for different lengths, the actual length of the bit shift register being determined by the data communication protocols employed.