Abstract: A multi-channel DSL communication link in accordance with the present invention may comprise a plurality of N DSL transceivers each configured with at least two bi-directional serial data interfaces with the first interface of a first transceiver coupled to a communication interface and the second interface of the first transceiver coupled to a first bi-directional serial data port of a second transceiver. Subsequent transceivers may be coupled in this manner with its Nth?1 and Nth+1 nearest transceivers. A method for transferring data between multiple transceivers is also disclosed, which can be described as follows: recovering a mapped portion of a downstream data stream at each of N DSL transceivers; communicating the portion to the next closest transceiver to a communication interface; and mapping an upstream data stream for transmission via the N transceivers; using each respective transceiver's second data interface to communicate a mapped portion to the next furthest transceiver.

Abstract: A single unified digital subscriber line (DSL) transceiver can be used for DSL applications, can be integrated on a single board or chip, or within a less board space. An embodiment of the unified DSL transceiver comprises a transmit circuit coupled to a line driver/transformer circuit. The line driver/transformer circuit is coupled to a receive circuit that comprises a switching circuit. A signal is transmitted from the transmit circuit to the line driver/transformer circuit; the switching circuit is configured based on DSL applications, and the signal is propagated from the line driver/transformer circuit to a line.

Abstract: A system for performing echo cancellation via use of a transceiver interface circuit. In a simplified embodiment, a digital signal processor (DSP), an analog front end (AFE), a line driver, and a hybrid network are located within the circuit. The DSP is configured to process a transmit, receive, and a transmit error signal. Mathematical operations of the DSP eliminate error from the receive signal with the help of the transmit error signal. The AFE modifies the transmit, receive, and transmit error signal from analog to digital or vice-versa. The line driver amplifies the transmit signal to a power level compatible with a transmission network. The line driver further produces the transmit error signal which is created by the amplification of the transmit signal. The hybrid network receives the amplified transmit signal from the AFE and a receive signal from the transmission network, and isolates the transmit signal from the receive signal.

Abstract: A method for combining trellis-coded modulation with one-bit constellations to make more efficient use of available channel capacity in discrete multitone (DMT) asymmetric digital subscriber line (ADSL) systems. Through fine transmit gain adjustment, in individual tones, DMT systems are able to compensate for truncation effects in bits-per-tone loading. However, the allowed fine gain adjustment range is insufficient to compensate for the DMT requirement that data modulated tones carry at least two bits. Therefore, by allowing data-modulated tones to carry a single bit, the available channel capacity can be more efficiently utilized. Additionally, one-bit constellations may be combined with trellis coded modulation. A pair of one-bit sub-carrier may be considered as a virtual two-bit sub-carrier in the trellis encoder with the resulting encoded bit pair transmitted on the original sub-carriers using one-bit constellations.

Abstract: The present invention is directed to an improved direct memory access (DMA) controller for executing commands having an improved instruction set. In accordance with one aspect of the present invention, a DMA controller is provided having an enhance command set. Specifically, a DMA controller is provided having the ability to perform a memory fill command. Thus, in accordance with one aspect of the invention, a method is provided for controlling a DMA controller to execute a memory fill command, wherein the method obtains a starting address, a segment length identifier, and a data value. Preferably, this information is obtained by reading successive bytes from external memory. The method then writes the data value to a plurality of consecutive locations in the memory, beginning at the starting address, wherein the number of consecutive locations written to is equal to the segment length identifier.

Abstract: A system and method for providing automatic compensation of IC design parameters that vary as a result of natural process variation is disclosed. In a simplified embodiment, the difference in voltages, &Dgr;VGS, between two identical diode-connected MOSFETs, which are biased with currents that are known to be different in value, is determined. &Dgr;VGS, is inversely proportional to the transconductance of the first of the two diode-connected MOSFETs, which is also biased with a current, ID. A relationship that embodies a direct proportionality between the transconductance of the first diode-connected MOSFET and a circuit performance parameter is derived, thereby establishing a relationship between &Dgr;VGS and the circuit performance parameter. Process compensation is then implemented, comparing known reference voltages with &Dgr;VGS.

Abstract: Disclosed is a configurable Reed-Solomon (RS) decoder that comprises a parallel multiply accumulator having a data input to receive at least one RS codeword, the parallel multiply accumulator being configured to generate a syndrome array from the RS codeword. The configurable RS decoder also includes a Galois field computation unit coupled to the parallel multiply accumulator, and an RS decoder controller coupled to the parallel multiply accumulator and the Galois field computation unit, wherein the RS decoder controller controls the operation of the parallel multiply accumulator and the Galois field computation unit. The RS decoder may be configured for different numbers of symbols in the RS codewords, parity symbols in the RS codewords, and modulation types employed in creating the RS codewords.

Abstract: A differential, two-stage op-amp circuit comprised of a plurality of electrically connected MOSFET's and including a telescopic op-amp circuit integrated with gain-boost amplifier circuits in the input stage and a fully-differential op-amp circuit in the output stage and having very high open-loop DC gain, very high unity-gain frequency, and considerably low power consumption is presented. The gain-boost amplifiers are configured as fully-differential op-amps, one being configured to be electrically connected to PMOS FET circuitry and the other being configured to be electrically connected to NMOS FET circuitry. The input stage op-amp circuit provides high gain, high input resistance, and large common mode rejection. The gain-boost op-amp circuits and the input stage form a local unity-gain feedback, and the outputs of the gain-boost op-amp circuits are adaptively stabilized. The output stage op-amp circuit provides gain, low output resistance, and minimal output loss.

Abstract: Disclosed is a system and method for signal conditioning and equalization in the time domain, preferably in a discrete multi-tone (DMT) modem. The system preferably includes a processor operating according to operating logic stored on a memory although a dedicated logical circuit may be employed. The operating logic includes logic executing the function of a low pass filter having a predetermined cutoff frequency configured to process a digitized data signal having a first sample rate f0, producing a filtered data signal at a second sample rate f1. The operating logic further includes logic which executes the function of a time domain equalizer, the time domain equalizer being configured to process the filtered signal to shorten the impulse response of the channel while at the same time, the time domain equalizer down-samples the filtered signal from the second sample rate f1, to a third sample rate f2 for further processing in the frequency domain.

Abstract: Disclosed is a configurable Reed-Solomon encoder and method. The configurable Reed-Solomon encoder comprises a multiplexed multiplier-accumulator, a parallel latch bank operatively coupled to the multiplexed multiplier-accumulator, a data/parity multiplexer coupled to the parallel latch bank, and an encoder controller operatively coupled to, and controlling the operation of, the multiplexed multiplier-accumulator, the parallel latch bank, and the data/parity multiplexer. The configurable Reed-Solomon encoder is preferably implemented in an application specific integrated circuit (ASIC), although it may be implemented in software executed by a high-speed digital signal processor, etc.

Abstract: The present invention is generally directed to a method for controlling the application of power to a line driver. The method operates by sensing a request from a customer premises for a transmission exchange across a local loop, applying power to a line driver circuit, in response to the request for transmission, determining when the transmission exchange has terminated, and then terminating the application of power to the line driver circuit.

Abstract: An improved line driver and method for increasing the available signal transmit power on a transmission line are disclosed. The improved line driver achieves an available transmit power increase without increasing the maximum current in the line driver output stage. The output stage of the line driver may comprise a first amplifier, a second amplifier, and an integrated back-matching resistor network. In order to further increase the available transmit power; a protective semiconductor device may be added to a line driver output stage for each semiconductor device in the first and second amplifiers. A third embodiment of a line driver output stage in accordance with the present invention may comprise a combination of the integrated back-matching resistor network along with the protective semiconductor devices.

Abstract: An improvement to system timing and synchronization in a digital transceiver allows the synchronization of a transceiver located at a central office to a network or system clock without the use of any additional transmitted bits or additional external circuitry. The system allows a transceiver to achieve timing and synchronization lock to a system master clock, such as a T1 or E1 clock, by operating on the two level input clock with a complex rotator to develop an error signal which allows a phase locked loop circuit to drive a frequency synthesizing device, which in turn drives a system clock. The system clock provides an input to a complex generator, which in turn develops a complex rotation function. The complex rotation function allows the transceiver clock to synchronize to the network master clock.

Abstract: A method for combining trellis-coded modulation with one-bit constellations to make more efficient use of available channel capacity in discrete multitone (DMT) asymmetric digital subscriber line (ADSL) systems. Through fine transmit gain adjustment, in individual tones, DMT systems are able to compensate for truncation effects in bits-per-tone loading. However, the allowed fine gain adjustment range is insufficient to compensate for the DMT requirement that data modulated tones carry at least two bits. Therefore, by allowing data-modulated tones to carry a single bit, the available channel capacity can be more efficiently utilized. Additionally, one-bit constellations may be combined with trellis coded modulation. A pair of one-bit sub-carrier may be considered as a virtual two-bit sub-carrier in the trellis encoder with the resulting encoded bit pair transmitted on the original sub-carriers using one-bit constellations.

Abstract: A system and method are disclosed for synchronizing a predetermined repeated data sequence contained in a first data signal at a first sample rate with the same predetermined repeated data sequence contained in a second data signal at a second sample rate in a data communications device. The system preferably includes a digital signal processor operating pursuant to logic stored on a memory. The logic includes synchronization logic which reduces the first sample rate to a predetermined correlation sample rate using a first decimator, resulting in a first reduced data signal. The synchronization logic also reduces the second sample rate to the same predetermined correlation sample rate using a second decimator, resulting in a second reduced data signal.

Abstract: The present invention is generally directed to a telephone handset for testing the transmission quality of a local loop. In accordance with one aspect of the invention, the telephone handset includes a connector configured to connect to the local loop at, for example, a junction box. The invention also includes a low-pass filter circuit electrically interposed between the connector and operational circuitry of the telephone handset. In operation, the low-pass filter is designed to pass (substantially undisturbed) electrical signals within the POTS frequency band from the connector to the operational circuitry. In the same way, the low-pass filter is designed to substantially block the passage of electrical signals above the POTS frequency range. In this way, the low-pass filter blocks the introduction of high frequency signals, which may otherwise generate intermodulation products within the audible range, from reaching the operational circuitry of the testing handset.

Abstract: In general, the multi-mode analog front-end provides an internal line driver and hybrid, as well as numerous functions, in order to provide a close to optimum solution for all digital subscriber line applications. The functions provided for by the analog front-end include; programmable hybrid attenuation; onboard amplifiers for driving external transmit and receive filters; a line driver with programmable drive and gain; programmable RC-filters capable of calibration via an internal loop-back under digital control; a programmable switched-capacitor filter for tracking the over sampling rate used by a digital signal processor; internal testing functions; a high frequency boost circuit; a dual input peak detector; selectable data rates; and a programmable data interface. The analog front-end allows for use of particular blocks within the analog front-end particular to the functions necessary to compensate for a particular digital subscriber line application.

Abstract: An improved SC filter for OSDACs for asynchronous digital subscriber line (ADSL) applications. More specifically, an improved switched-capacitance (SC) filter for an over-sampled digital to analog converter intended for use in a multi-mode analog front end for a host of ADSL applications. The SC filter is configured for low power consumption and for a low-ambient noise floor across the frequencies of interest. The SC filter is further configured to drive a resistive load of a few kohms and for low signal distortion. The SC filter lowers power consumption by decimating the input waveform and reducing the number of operational amplifiers in the circuit.

Abstract: A system and method for modifying symbol duration for the efficient transmission of information in a time duplex noise environment is disclosed. In a simplified embodiment, the system modifies the length of Discrete MultiTone (DMT) symbols, thereby providing a system wherein a first half of the DMT symbols are transmitted entirely during a period in which there is far end crosstalk (FEXT) noise, and a second half of the DMT symbols are transmitted entirely during a period in which there is near end crosstalk (NEXT) noise. Preferably, the duration of each DMT symbol is selected to be 0.25 ms such that exactly ten DMT symbols fall within a time duplex period of 2.5 ms. As such, during a FEXT period, exactly five DMT symbols are transmitted, and during a NEXT period, exactly five DMT symbols are transmitted. Therefore, in each TTR period, an additional DMT symbol, with modified length, is transmitted during the FEXT period, during which information is transmitted at a high bit rate.

Abstract: In general, the system and method provides a balanced clock distribution between two devices. A first output buffer, located in a source chip, provides buffering of a clock signal, after which, the delayed clock signal is transmitted to a destination chip, as well as to a balancing buffer located in the source chip. In addition, a second buffer, also located in the source chip, provides buffering of a data signal, after which, the data signal is transmitted to the destination chip. Both the clock and the data signals are then further buffered by first and second input buffers respectfully, which are located on the destination chip. After the delayed clock signal has been received by the balancing buffer, the balancing buffer provides a balancing delay to the delayed clock signal in accordance with the delay provided by the first input buffer, located in the destination chip, so as to provide a balanced clock distribution between the source chip and the destination chip.