Abstract: A communication system is disclosed in which information is transmitted using DMT modulation. The communication system includes first logic that is used to measure the response of each of the DMT subchannels and second logic that is used to adapt an equalizer filter associated with each of the DMT channels based on the response measurements. The system further includes third logic that measures the noise variance for each of the DMT subchannels. Using the noise variance measurements, fourth logic is used to assign the number of bits for transmission on each DMT subchannel such that total transmit power is minimized for a fixed data rate. Equations are provided for calculating a near optimal bit load allocation for the DMT subchannels and for calculating the total number of bits to be allocated to the DMT subchannels in a single encoding interval when total transmission power is limited.

Abstract: The present invention is generally directed to a power control circuit for a line driver circuit in a central office. In a broad sense, the present invention operates to power-down line driver circuitry when it is not in use, and apply power to the line driver circuitry when transmissions are requested by a customer (e.g., customer premises). This reduces the power consumption of the line driver by eliminating the quiescent current draw when the line driver is idle. Recognizing that the typical line driver is in an idle state the vast majority of the time, compounded by the vast number of line drivers that exist within a central office environment, it will be appreciated that the overall power savings may be tremendous. In accordance with one aspect of the invention a circuit is provided for controllably applying power to a line driver.

Abstract: The present invention provides a switched impedance matching network which may be implemented in a hybrid circuit of a digital subscriber line (DSL) system, or in any other wire-bound communications system for which two-wire-to-four-wire conversion, and vice versa, must be accomplished. In accordance with the preferred embodiment of the present invention, the matching network comprises switchable circuit modules of discrete-valued resistor and capacitor components. Preferably, the circuit modules are assembled into an array of buffered first-order RC circuits. The buffers comprise amplifiers that are switched on or off to control the switching of the circuit modules. The buffer amplifiers also isolate the individual circuit modules from each other and eliminate the need to implement transmission switches between the modules. The switching of the buffer amplifiers clears or blocks the transmission paths between the individual modules, thereby providing the optimum path through the module array.

Abstract: A system and method which establishes an optimum margin for each channel in a discrete multi-tone (DMT) transceiver. The present system entails a discrete multi-tone transceiver which comprises a processor and a memory. Stored on the memory is operating logic which directs the function of the processor. The operating logic includes bit allocation logic and signal-to-noise (SNR) variation logic. The SNR variation logic determines an variation in the signal-to-noise ratio for each channel. The bit loading logic then determines a bit loading configuration based upon the variation in the signal-to-noise ratio ascertained by the SNR variation logic. The SNR variation logic preferably includes logic to determine the variation in the signal-to-noise ratio by means of statistical analysis, however, other approaches to determining the variation in the signal-to-noise ratio may be employed.

Abstract: The present invention entails a circuit and method for determining the distortion created by a transformer used in data communications. The circuit according to the present invention comprises a transmitting circuit, a back matching circuit, and a subtracting circuit. The transmitting circuit generates a test signal to be transmitted into a transformer, the transmitting circuit having a transmitting output for coupling to a transformer. Once applied to the transformer, the test signal is distorted by the transformer, where the transformer creates harmonics of the test signal and other signal distortion. The back matching circuit generates a scaled test signal that is subtracted from the distorted test signal in the subtraction circuit. The result is a diminished peak at the test signal in comparison to the harmonics such that the distortion by the transformer can be determined using a measuring device with a relatively low dynamic range.

Abstract: An line interface circuit at a central office of a telecommunication system provides improved noise immunity to a ring signal. In accordance with one aspect of the invention, the line interface circuit includes a signal line having a first end for connection to a ring signal generating source and a second end for communication with a customer premises via a local loop. A POTS filter is electrically connected to the signal line. Preferably, the POTS filter is a relatively simple and thus inexpensive low-order filter, which may be implemented as a simple L-C circuit. The preferred embodiment of the present invention further includes a POTS communication device electrically connected to the signal line at a point between the POTS filter and the first end. In this regard, the POTS communications device broadly denotes any device designed to communicate information within the POTS frequency band, such as a telephone (e.g., voice information), a facsimile machine, a PSTN modem, etc.

Abstract: A system and method for demodulating digital information from a modulated signal that can be represented in a signal space diagram as an odd constellation of sample points. The system comprises filtering means for receiving the modulated signal that includes means for rotating the received sample points 45.degree. clockwise on the signal space diagram such that decision or neighborhood regions can be drawn having borders that are either parallel or perpendicular to the axes of the signal space diagram. As a result, a slicer can easily extract the symbol information from the rotated sample points with a minimum of computational complexity. Moreover, and perhaps most importantly, the rotation is accomplished through a one time modification of the tap coefficients used by the filtering means thus eliminating any additional processor real time required to perform the rotation.

Abstract: The present invention is generally directed to a multi-mode buffer that is configurable to control output delivered to an input, with a variable clock cycle delay. For example, the buffer may be controlled, in one mode to deliver input data to an output, at a one clock cycle delay (i.e., output data at next clock edge). In another mode, the buffer may be controlled to deliver input data to an output, at a two clock cycle delay. In accordance with one aspect of the present invention, the buffer includes a clock input, a data input, a control input, and an output. The input and the output may be of variable bit width. For example, 8 bits, 16 bits, or some other bit width. The buffer further includes circuitry for delivering data on the data input to the output in response to the clock input.

Abstract: A system for the evaluation of a timing vector to determine whether reliable timing recovery may be established at a predetermined center frequency, or from a specific pilot tone in the received signal. According to the present invention, the timing vector is created using band edge filters, a pilot tone timing recovery band pass filter, or other suitable means. The timing vector is then sampled a predetermined number of times. The sampled timing vectors are plotted on a complex plane to evaluate the general distribution of the sampled timing vectors. Timing recovery is then established using an acceptable timing vector as determined by comparing the distribution of the sampled vectors with a predetermined distribution threshold. In particular, a narrow distribution indicates minimum of signal noise, interference, or disruption, whereas a wide distribution indicates the opposite.

Abstract: A DSL communication device wherein the state of component coefficients are saved in a memory of a DSL device so that at a later time, the DSL device may initiate a warm start activation sequence wherein the last known channel parameters are used to train the equalizer, significantly reducing the amount of equalizer training required by eliminating the requirement that the aforementioned coefficients be transferred between DSL devices.