Patents Assigned to GlobespanVirata Incorporated
  • Patent number: 7013271
    Abstract: A method and system for implementing a low complexity spectrum estimation technique for comfort noise generation are disclosed. Another aspect of the present invention involves segregating filter parameter encoding from an adaptation process for transmission in the form of silence insertion descriptors. A method for implementing a spectrum estimation for comfort noise generation comprises the steps of receiving an input noise signal; approximating a spectrum of the input noise signal using an algorithm over a period of time; detecting an absence of speech signals; and generating comfort noise based on the approximating step when the absence of speech signals is detected; wherein the spectrum of the input noise signal is substantially constant over the period of time.
    Type: Grant
    Filed: June 5, 2002
    Date of Patent: March 14, 2006
    Assignee: GlobespanVirata Incorporated
    Inventor: Vasudev S. Nayak
  • Patent number: 6961779
    Abstract: A system and method is provided for facilitating robust reception of multiple frame protocol messages. Initially, a first frame of data is received including therein a first segment of a multi-frame protocol message. Next, the received frame is placed into a data buffer. The buffer is then examined and the message contained therein is parsed to determine whether the received message is a complete message or not. If it is determined that the received message contained in the buffer is an incomplete message, a continuation message is sent to the remote transceiver ATU. However, if the message is determined to be complete, the message is parsed again and the complete message information contained therein is extracted and processed in accordance with the handshaking requirements. Upon receipt of the next frame in the message, this frame is concatenated onto the existing frames in the data buffer. The entire buffer is then re-parsed to determine its completeness.
    Type: Grant
    Filed: February 11, 2002
    Date of Patent: November 1, 2005
    Assignee: Globespanvirata, Incorporated
    Inventor: Herbert Lyvirn Lacey, III
  • Patent number: 6952430
    Abstract: A system and method is provided for interfacing a protocol component with a physical layer component. Initially, a parameter setting message is sent to the physical layer indicating at least the mode of the processor. If the mode is nonframing, a handshaking tone or pattern detection request message is sent to the physical layer component enabling detection of specific handshaking tones or patterns. Next, a handshaking tone or pattern detection indicate message is received from the physical layer component indicating that a recognized tone or bit pattern has been detected in response to a detection request message. A signal request message is sent from the handshaking component to the physical layer component indicating that a handshaking message is to be transmitted as well as the content of that message. In addition, the signal request message also preferably includes parameters relating to the duration of the signal to be transmitted, such as a maximum and minimum symbol number.
    Type: Grant
    Filed: February 12, 2002
    Date of Patent: October 4, 2005
    Assignee: Globespanvirata Incorporated
    Inventor: Herbert Lyvirn Lacey, III
  • Patent number: 6931343
    Abstract: An on-signal calibration system I and Q signals of a transmitter to remove distortions in the RF output signal. The transmitter generates I and Q values and converts, modulates and combines the I and Q values into the RF output signal for transmission. The calibration system includes a detector, a sampler, a selector, an imbalance estimator, and an IQ corrector. The detector senses the RF output signal and provides a detection signal indicative thereof. The sampler samples the detection signal and provides digital samples. The selector selects from among the digital samples that correspond to predetermined ranges of the I and Q values, or otherwise predetermined selection boxes at predetermined phases. The imbalance estimator determines at least one imbalance estimate based on selected digital samples. The IQ corrector corrects the I and Q values using at least one imbalance estimate.
    Type: Grant
    Filed: September 19, 2003
    Date of Patent: August 16, 2005
    Assignee: Globespanvirata, Incorporated
    Inventors: Mark A. Webster, Michael J. Seals, Bruce A. Cochran
  • Patent number: 6854025
    Abstract: A DMA scheduling mechanism for transmission of fragmented buffers having a processor for controlling several devices via a polled interface to interleave DMA data transfers on different Input/Output (I/O) ports in an efficient manner. The system handles transmission of network packets which are reassembled from multiple memory buffers with different octet alignments is provided. The hardware/software combination allows efficient joining of packet fragments with differing octet alignments when the underlying memory system is word based, and further allows insertion of other data fields generated by a processor.
    Type: Grant
    Filed: July 8, 2003
    Date of Patent: February 8, 2005
    Assignee: GlobespanVirata Incorporated
    Inventors: Brian Knight, David Milway
  • Publication number: 20040218667
    Abstract: A “Smart DSL System” for addressing the performance objectives of LDSL and examples of smart systems for LDSL are disclosed. In accordance with embodiments of the invention, there is disclosed a method for implementing smart DSL for LDSL systems. Embodiments of the method include presenting a number of spectral masks that are available on the LDSL system, and selecting from the number of spectral masks an upstream mask and a downstream mask wherein the upstream mask and the downstream mask exhibit complimentary features.
    Type: Application
    Filed: November 18, 2003
    Publication date: November 4, 2004
    Applicant: GlobespanVirata Incorporated
    Inventors: Patrick Duvaut, Lujing Cai, Massimo Sorbara
  • Publication number: 20040194085
    Abstract: There is provided a method and system for facilitating the allocation and management of system resource modules. Applications request services directly from a controlling library rather than directly from the resource. Initially, system service providers register capabilities and relative priorities with the controlling library. Following registration, the controlling library will receive all service requests from applications. In response, the controlling library identifies the available resource having the highest priority and passes the service request to that resource.
    Type: Application
    Filed: May 9, 2002
    Publication date: September 30, 2004
    Applicant: GlobespanVirata Incorporated
    Inventors: Eric Beaubien, Kraig Eric Haglund, Michael Goldflam
  • Patent number: 6770493
    Abstract: An integrated circuit design is provided capable of operating in multiple insertion orientations. In particular, the inventive circuit design includes an integrated circuit package having a plurality of contact elements extending from the integrated circuit package and arranged symmetrically thereon for enabling the integrated circuit to be inserted on a circuit board in at least two discrete orientations. A plurality of the contact elements are designated as orientation pins, the orientation pins being arranged such that, upon integrated circuit package power up, the orientation pins transmit orientation signals indicative of the integrated circuit packages insertion orientation in the circuit board. A plurality of multiplexer devices are provided for routing signals between the contact elements and integrated circuit functional circuitry in response to the orientation signals from the orientation pins.
    Type: Grant
    Filed: July 16, 2003
    Date of Patent: August 3, 2004
    Assignee: GlobespanVirata, Incorporated
    Inventor: David Stuart Baker
  • Publication number: 20040136534
    Abstract: Mechanisms for providing a subscriber-side interface with a passive optical network are described herein. An optical network termination (ONT) having an integrated broadband passive optical network processor is utilized to receive downstream data from an optical line termination (OLT) via a passive optical network and provide the contents of the downstream data to one or more subscriber devices via one or more data interfaces. Similarly, the ONT is adapted to receive and transmit upstream data from the one or more subscriber devices to the OLT via the passive optical network. The ONT preferably implements one or more encryption/decryption mechanisms, such as the digital encryption standard (DES), to provide data protection in addition to, or in place of, data churning provided for by the ITU G.983 recommendations.
    Type: Application
    Filed: January 13, 2003
    Publication date: July 15, 2004
    Applicant: GlobespanVirata Incorporated
    Inventors: James Stiscia, Raymond Chen
  • Patent number: 6756656
    Abstract: Inducting devices having a patterned ground shield with ribbing in an integrated circuit. In one embodiment, an inducting device comprises conductive turns to conduct current, a shield layer and a plurality of ribs. The shield layer is formed a select distance from the conductive turns. The shield layer is patterned into sections of shield to prevent eddy currents. The plurality of ribs are formed from a conductive layer that is positioned between the conductive turns and shield layer. Each rib is electrically coupled to a single associated section of shield. Moreover, each rib is more conductive than its associated section of shield to provide a less resistive current path than its associated section of shield.
    Type: Grant
    Filed: July 11, 2002
    Date of Patent: June 29, 2004
    Assignee: GlobespanVirata Incorporated
    Inventor: Rex Everett Lowther
  • Publication number: 20040071133
    Abstract: An exemplary mechanism for intelligent Point-to-Point Protocol over Ethernet (PPPoE) initialization is disclosed herein. During the PPPoE discovery stage, a PPPoE client of a CPE determines the status of a connection between the CPE and an access concentrator prior to transmitting a PADI and/or PADR packet. If a physical layer connection is established, the PPPoE client can provide the packet to the physical interface for transmission to the access concentrator. If a physical layer connection is not established, the PPPoE client either periodically rechecks the status of the connection until a physical layer connection is established or the PPPoE can terminate the PPPoE discovery stage after a certain number of iterations. Additionally, prior to waiting for a PADO or PADS packet, the PPPoE client can be adapted to check the status of the connection. If a physical layer connection exists, the PPPoE client can initiate the wait for the packet.
    Type: Application
    Filed: October 11, 2002
    Publication date: April 15, 2004
    Applicant: GlobespanVirata Incorporated
    Inventors: Jon A. Yusko, Kraig E. Haglund
  • Publication number: 20040008730
    Abstract: A system and method for improved synchronous access of stored data are provided herein. A data requestor transmits a clock signal and a read request signal for reception by a data source, whereupon skewed versions of the clock signal and the read request signal are received due to the delays in the signal paths between the data requestor and the data source. Accordingly, the data requestor provides skewed clock and read request signals to its input sampling module to simulate the delays of the signal paths. Additionally, the data requestor provides process information associated with the requested data to a dual clock first in-first out (FIFO) buffer. When the input sampling module detects a read request using the skewed read request signal, the input sampling module can use this signal and the skewed clock signal to sample a data signal from the data source to obtain the requested data.
    Type: Application
    Filed: July 15, 2002
    Publication date: January 15, 2004
    Applicant: GlobespanVirata Incorporated
    Inventor: Amir Helzer
  • Publication number: 20030235150
    Abstract: A system and method for formatting and transmitting DMT symbols. For each symbol to be transmitted, the last Lcp samples of the symbol are prepended to the symbol as a cyclic prefix. Next, of the samples contained within the cyclic prefix, the first Î2 samples are appended to the symbol as a cyclic suffix. By providing the above described cyclic prefix and suffix, sharp PSD transitions are provided in the first overlapped RFI band (1.8-2 MHz) and out of band PSD. Upon formatting, each symbol is transmitted so that its transmission overlaps the prior symbol by Î2 samples. This results in the output signal being shaped by a raised cosine function for the duration of the Î2 overlap.
    Type: Application
    Filed: June 16, 2003
    Publication date: December 25, 2003
    Applicant: GLOBESPANVIRATA INCORPORATED
    Inventor: Albert Rapaport
  • Patent number: 6667561
    Abstract: An integrated circuit design is provided capable of operating in multiple insertion orientations. In particular, the inventive circuit design includes an integrated circuit package having a plurality of contact elements extending from the integrated circuit package and arranged symmetrically thereon for enabling the integrated circuit to be inserted on a circuit board in at least two discrete orientations. A plurality of the contact elements are designated as orientation pins, the orientation pins being arranged such that, upon integrated circuit package power up, the orientation pins transmit orientation signals indicative of the integrated circuit packages insertion orientation in the circuit board. A plurality of multiplexer devices are provided for routing signals between the contact elements and integrated circuit functional circuitry in response to the orientation signals from the orientation pins.
    Type: Grant
    Filed: March 13, 2002
    Date of Patent: December 23, 2003
    Assignee: GlobespanVirata, Incorporated
    Inventor: David Stuart Baker
  • Publication number: 20030210696
    Abstract: A method and a system for using a network switch, such as in a gateway, to route frames between network segments are disclosed. Frames from one network segment can be provided to one of a plurality of ports of a network switch. The network switch provides the frames to a processor, whereupon the processor performs any higher-level processing of the frames, such as Internet Protocol Security (IPSec) or network address translation (NAT). After any applicable modification of the frame the processor provides the modified frame back to the network switch for output on a port associated with a network segment that includes the intended destination of the frame.
    Type: Application
    Filed: April 25, 2002
    Publication date: November 13, 2003
    Applicant: GlobespanVirata Incorporated
    Inventor: Michael S. Goldflam
  • Publication number: 20030204636
    Abstract: Systems and methods are provided for implementing: a rings architecture for communications and data handling systems; an enumeration process for automatically configuring the ring topology; automatic routing of messages through bridges; extending a ring topology to external devices; write-ahead functionality to promote efficiency; wait-till-reset operation resumption; in-vivo scan through rings topology; staggered clocking arrangement; and stray message detection and eradication. Other inventive elements conveyed include: an architectural overview of a packet processor; a programming model for a packet processor; an instruction pipeline for a packet processor; and use of a packet processor as a module on a rings-based architecture.
    Type: Application
    Filed: July 2, 2002
    Publication date: October 30, 2003
    Applicant: GlobespanVirata Incorporated
    Inventors: Ilia Greenblat, Moshe Rafaeli, Elizer Weitz
  • Publication number: 20030200339
    Abstract: Systems and methods are provided for implementing: a rings architecture for communications and data handling systems; an enumeration process for automatically configuring the ring topology; automatic routing of messages through bridges; extending a ring topology to external devices; write-ahead functionality to promote efficiency; wait-till-reset operation resumption; in-vivo scan through rings topology; staggered clocking arrangement; and stray message detection and eradication. Other inventive elements conveyed include: an architectural overview of a packet processor; a programming model for a packet processor; an instruction pipeline for a packet processor; and use of a packet processor as a module on a rings-based architecture.
    Type: Application
    Filed: July 2, 2002
    Publication date: October 23, 2003
    Applicant: GlobespanVirata Incorporated
    Inventors: Ilia Greenblat, Moshe Tarrab, Uri Trichter, Oded Norman, Boris Zabarski, Moshe Refaeli, Elizer Weitz
  • Publication number: 20030195991
    Abstract: Systems and methods are provided for implementing: a rings architecture for communications and data handling systems; an enumeration process for automatically configuring the ring topology; automatic routing of messages through bridges; extending a ring topology to external devices; write-ahead functionality to promote efficiency; wait-till-reset operation resumption; in-vivo scan through rings topology; staggered clocking arrangement; and stray message detection and eradication. Other inventive elements conveyed include: an architectural overview of a packet processor; a programming model for a packet processor; an instruction pipeline for a packet processor; and use of a packet processor as a module on a rings-based architecture.
    Type: Application
    Filed: July 2, 2002
    Publication date: October 16, 2003
    Applicant: GlobespanVirata Incorporated
    Inventors: Jonathan Masel, Boris Zabarski, Ilia Greenblat
  • Publication number: 20030191863
    Abstract: Systems and methods are provided for implementing: a rings architecture for communications and data handling systems; an enumeration process for automatically configuring the ring topology; automatic routing of messages through bridges; extending a ring topology to external devices; write-ahead functionality to promote efficiency; wait-till-reset operation resumption; in-vivo scan through rings topology; staggered clocking arrangement; and stray message detection and eradication. Other inventive elements conveyed include: an architectural overview of a packet processor; a programming model for a packet processor; an instruction pipeline for a packet processor; and use of a packet processor as a module on a rings-based architecture.
    Type: Application
    Filed: July 2, 2002
    Publication date: October 9, 2003
    Applicant: GlobespanVirata Incorporated
    Inventor: Ilia Greenblat
  • Publication number: 20030191861
    Abstract: Systems and methods are provided for implementing: a rings architecture for communications and data handling systems; an enumeration process for automatically configuring the ring topology; automatic routing of messages through bridges; extending a ring topology to external devices; write-ahead functionality to promote efficiency; wait-till-reset operation resumption; in-vivo scan through rings topology; staggered clocking arrangement; and stray message detection and eradication. Other inventive elements conveyed include: an architectural overview of a packet processor; a programming model for a packet processor; an instruction pipeline for a packet processor; and use of a packet processor as a module on a rings-based architecture.
    Type: Application
    Filed: July 2, 2002
    Publication date: October 9, 2003
    Applicant: GlobespanVirata Incorporated
    Inventor: Ilia Greenblat