Abstract: A memory cell, an array of memory cells, and a method for fabricating a memory cell with multigate transistors such as fully depleted finFET or nano-wire transistors in embedded DRAM. The memory cell includes a trench capacitor, a non-planar transistor, and a self-aligned silicide interconnect electrically coupling the trench capacitor to the non-planar transistor.
Type:
Grant
Filed:
October 17, 2011
Date of Patent:
June 14, 2016
Assignee:
GlogalFoundries, Inc.
Inventors:
Josephine B. Chang, Leland Chang, Michael A. Guillorn, Wilfried E. Haensch