Patents Assigned to Gold Star Electron Co., Ltd.
  • Patent number: 5314298
    Abstract: This invention relates to an automatic lead frame feeding device for a TO-220 semiconductor manufacturing apparatus, which automatically feeds lead frames to die bonding and wire bonding processes for manufacturing TO-220 semiconductor packages, and has an object to provide an automatic lead frame feeding device which can load large quantities of lead frames at a time without using a separate magazine for loading them, and then feed automatically them accurately one by one. To this end, the feeding device includes a loading section including a pair of guide members disposed in spaced opposite relation to each other to stack up lead frames therebetween, a transferring section disposed at one side of the loading section for transverse movement to drop one by one the stacked lead frames in the loading section in sequence beginning with the lowermost lead frame, and a feeding section positioned to feed the dropped lead frame in the loading section to a subsequent process.
    Type: Grant
    Filed: May 22, 1992
    Date of Patent: May 24, 1994
    Assignee: Gold Star Electron Co., Ltd.
    Inventor: Youl Kim
  • Patent number: 5313080
    Abstract: A p type well is formed on an n type substrate and photodiode and VCCD regions are repeatedly at predetermined intervals in turns on the surface of the p type well.In an interline transfer image sensor, the p type well is formed on the n type substrate and the photodiode and VCCD region of predetermined intervals are repeatedly formed in turn on the surface of the p type well. The p.sup.+ type channel ion stop layer is formed at both edges of the VCCD region and the pinning voltage is applied to the p.sup.+ type channel stop layer. Accordingly, the variable potential of the potential contour of the VCCD region is increased and the storing capacity of the charge and the efficiency of the charge transfer are maximized side by side.
    Type: Grant
    Filed: July 27, 1993
    Date of Patent: May 17, 1994
    Assignee: Gold Star Electron Co., Ltd.
    Inventor: Hun J. Jung
  • Patent number: 5313520
    Abstract: A method and a device are provided for protecting data stored in a ROM of a micoprogram control unit. Such data may take the form of a user program. To protect the data, predetermined code data is written into a predetermined address in the ROM. A code address inputted from outside the microprogram control unit is then compared with the predetermined address. If the inputted code address is determined to match the predetermined address, then code data inputted from outside the microprogram control unit is compared with the predetermined code data. Only after both of these comparisons are successfully made is the data in the ROM allowed to be read outside the microprogram control unit.
    Type: Grant
    Filed: January 29, 1993
    Date of Patent: May 17, 1994
    Assignee: Gold Star Electron Co., Ltd.
    Inventor: Dae K. Han
  • Patent number: 5300377
    Abstract: In order to manufacture a phase shift mask for hyperfine patterning, a sidewall phase shift mask is formed on both sides of each phase shift film in a spatial frequency modulation type phase shift mask. Accordingly, the light intensity occurring from the end part of the phase shift film, as the forming factor of the bridge pattern film, is reduced by the sidewall phase shift film.
    Type: Grant
    Filed: May 7, 1992
    Date of Patent: April 5, 1994
    Assignee: Gold Star Electron Co., Ltd.
    Inventor: Eun S. Keum
  • Patent number: 5298777
    Abstract: A CCD image sensor of an interlaced scanning type comprising a plurality of uniformly spaced photodetectors arranged in series in vertical and horizontal directions, a plurality of VCCD regions arranged between sets of said photodetectors arranged in the vertical directions, a plurality of channel stop regions for electrically isolating said plurality of photodetectors from one another, a plurality of gate electrodes formed on said VCCD regions, each of said plurality of gate electrodes being connected simultaneously to transfer gate electrodes of adjacent ones of said plurality of photodetectors on odd and even horizontal lines, a plurality of barrier layers, each formed at a portion of each of said VCCD regions corresponding to a boundary with each of said gate electrodes on said VCCD regions, for forming a desired potential barrier, and a HCCD region formed under said plurality of VCCD regions, for transferring signal charges from said VCCD regions to an output stage.
    Type: Grant
    Filed: July 27, 1993
    Date of Patent: March 29, 1994
    Assignee: Gold Star Electron Co., Ltd.
    Inventor: Seo K. Lee
  • Patent number: 5276341
    Abstract: The present invention relates to a structure and a method for fabrication of a CCD image sensor having a structure that a p-type epitaxial layer is formed on an n-type substrate to reduce a smear noise and an n-type region for controlling an OFD voltage which is disposed between an n-type substrate beneath an n-type photo diode and a p-type epitaxial layer and a p.sup.+ -type region for reducing the smear phenomenon which is deposed between an n-type substrate beneath an n-type BCCD and a p-type epitaxial layer. According to this improved structure and method, it can be fabricated of a CCD image sensor easily and rapidly and with reduced smear noise.
    Type: Grant
    Filed: January 29, 1993
    Date of Patent: January 4, 1994
    Assignee: Gold Star Electron Co., Ltd.
    Inventor: Sung M. Lee
  • Patent number: 5274476
    Abstract: A CCD image sensor having a plurality of VCCDs each formed in a zig-zag pattern in a vertical direction and a plurality of groups of first to fourth photodiodes, the first to fourth photodiodes of the respective groups being arranged respectively on the left and right sides of each of the VCCDs, so that an improvement in resolution of a picture can be made in the same chip size. The first photodiodes are arranged on the left sides of curved portions of each of the VCCD regions on odd horizontal scanning lines, the second photodiodes are arranged on the right sides of the curved portions of each of the VCCD regions on even horizontal scanning lines, the third photodiodes are arranged on the right sides of the curved portions of each of the VCCD regions on the odd horizontal scanning lines, and the fourth photodiodes are arranged on the left sides of the curved portions of each of the VCCD regions on the even horizontal scanning lines.
    Type: Grant
    Filed: August 11, 1992
    Date of Patent: December 28, 1993
    Assignee: Gold Star Electron Co., Ltd.
    Inventor: Sung M. Lee
  • Patent number: 5270257
    Abstract: A method of making a metal oxide semiconductor field effect transistor. An oxide layer is grown on the overall exposed surface of a substrate, which then has a trench formed by an etching process. A polysilicon layer is deposited on the trenched substrate, by using a nitride layer formed on the substrate as a mask, to form a gate region of a predetermined thickness. Then, the nitride layer is removed. The exposed portion of the polysilicon gate layer is then oxidized. Then, the exposed portion of the silicon substrate, disposed at opposite sides of the gate electrode, is subjected to a low concentration n-type ion injection, to form low concentration drain and source regions. Then, an oxide side wall is formed to surround the gate electrode. The exposed surface of the silicon substrate, disposed at opposite sides of the gate electrode, is subjected to a high concentration n-type ion injection.
    Type: Grant
    Filed: May 15, 1992
    Date of Patent: December 14, 1993
    Assignee: Gold Star Electron Co., Ltd.
    Inventor: Hyung S. Shin
  • Patent number: 5262337
    Abstract: A metal oxide semiconductor field effect transistor (MOSFET) and a method of making the same, capable of avoiding the generating of a high horizontal electric field in low concentration source and drain regions. In accordance with the invention, a p-type substrate is patterned to form a channel region of a convex type thereon. At opposite side portions of the channel region, low concentration source and drain regions are formed which is in turn covered with a gate. High concentration source and drain regions are formed in the portions of the substrate disposed outwardly of opposite side portions of the gate and near the surface of the substrate. Electric fields of low concentration source and drain regions can be controlled by the gate, since the regions are connected to the gate, via the gate oxide layer. As a result, it is possible to avoid the generation of a high horizontal electric field in low concentration source and drain regions.
    Type: Grant
    Filed: March 11, 1992
    Date of Patent: November 16, 1993
    Assignee: Gold Star Electron Co., Ltd.
    Inventor: SHi H. Kim
  • Patent number: 5256591
    Abstract: A method for forming an isolation region in a semiconductor device using a trench comprising the steps of forming a reaction restraining layer on a semiconductor substrate, removing a portion of the reaction restraining layer corresponding to a trench region for providing an isolation region, forming a reaction film on the entire exposed surface, heat treating the reaction film and the substrate, to form a reaction product film having a predetermined depth in a portion of the reaction film and a portion of the substrate corresponding to said trench region, etching and removing the reaction product film, to form a trench, forming an insulation film for the isolation region such that it fills sufficiently the trench, forming a surface smoothing insulation film on the insulation film for the isolation region, etching back both the insulation films such that their portions located above a predetermined height from the surface of the substrate are removed, and removing the remaining reaction restraining layer.
    Type: Grant
    Filed: June 12, 1992
    Date of Patent: October 26, 1993
    Assignee: Gold Star Electron Co., Ltd.
    Inventor: Young K. Jun
  • Patent number: 5245470
    Abstract: The present invention relates to a polarizing exposure apparatus using a polarizer for radiating polarized light on a polarizing mask and a method for a polarizing mask, for improved resolution, by using such a polarizing exposure apparatus. The polarizing exposure apparatus using a polarizer comprises a light source for radiating light, a pair of polarizing plates for respectively polarizing light radiated from the light source, a focusing lens for focusing the light polarized through said polarizing plates, a polarizing mask for passing only light of the desired pattern from the polarized light focused through the focusing lens and a reduction projection lens for forming the pattern on a wafer by reducing the light passed through the polarizing mask.
    Type: Grant
    Filed: March 2, 1992
    Date of Patent: September 14, 1993
    Assignee: Gold Star Electron Co., Ltd.
    Inventor: Eun S. Keum
  • Patent number: 5236076
    Abstract: An apparatus for automatically unloading devices in handler which fills empty sleeves with devices tested from a tester and unloads the sleeves according to characteristics of the devices, and which can selectively actuate a plurality of stopper pins by only one output signal without a plurality of solenoids. The apparatus comprises a multitray having a plurality of tracks which is positioned above a guide shaft of the handler, a plurality of followers, each having a stopper pin for blocking and releasing devices on the tracks, which are mounted on the corresponding tracks respectively, an arm mounted on a slide block slidably mounted on the guide shaft which comes into contact with one of the followers selectively, and an operating plate for raising and lowering the arm and one of the followers by actuation of a cylinder.
    Type: Grant
    Filed: September 8, 1992
    Date of Patent: August 17, 1993
    Assignee: Gold Star Electron Co., Ltd.
    Inventor: Yong G. Sung
  • Patent number: 5233429
    Abstract: A CCD image sensor having an N type photodetecting region, an N type VCCD region and an N type HCCD region, comprising a P type layer formed underneath and surrounding said N type VCCD region, an N type layer formed underneath and surrounding said P type layer, a P type well formed underneath and surrounding said N type layer, and an N type substrate formed under said P type well, said substrate being adapted and arranged for the application thereto of a shutter voltage. In accordance with the present invention, the CCD image sensor is capable of preventing an overflow drain caused by error charges or excess charges resulting from a smear. Therefore, the photoelectric efficiency can be increased in a wavelength of the red color type wherein the amount of light energy is small.
    Type: Grant
    Filed: October 11, 1991
    Date of Patent: August 3, 1993
    Assignee: Gold Star Electron Co. Ltd.
    Inventor: Hun J. Jung
  • Patent number: 5229315
    Abstract: The present invention relates to a method for forming an isolated film on a semiconductor device in the shape of a cylinder to shorten the heat treatment process and to prevent a micro-loading effect of filling of a field-isolated oxide film. The method comprises the step of forming a deep, narrow groove, then filling up the groove with an oxide film, and then oxidizing a polysilicon layer encircled by the groove to form an isolated film in the shape of a cylinder.
    Type: Grant
    Filed: January 16, 1992
    Date of Patent: July 20, 1993
    Assignee: Gold Star Electron Co., Ltd.
    Inventors: Young K. Jun, Young S. Kim
  • Patent number: 5219777
    Abstract: A MOSFET comprising a substrate of a first conductivity type, a gate located on the substrate, a channel region of the first conductivity type located beneath a surface portion of the substrate corresponding to a region defined beneath said gate, low concentration and high concentration source regions of a second conductivity type located beneath a surface portion of the substrate corresponding to one of opposite sides of said channel region, and low concentration and high concentration drain regions of the second conductivity type located beneath a surface portion of the substrate corresponding to the other of opposite sides of the channel region. A pair of first impurity regions of the first conductivity type are located to surround said second conductivity type low concentration source region and said second conductivity type low concentration drain region respectively.
    Type: Grant
    Filed: June 11, 1992
    Date of Patent: June 15, 1993
    Assignee: Gold Star Electron Co., Ltd.
    Inventor: Dae K. Kang
  • Patent number: 5219780
    Abstract: The present invention relates to a method for fabricating a semiconductor memory cell consisting of a switching transistor and a capacitor wherein a polysilicon pad and a polysilicon storage node are simultaneously patterned with a self-alignment method without a mask.Accordingly, the present invention has the following advantages: First, the overlay accuracy can be improved by patterning a polysilicon pad and a polysilicon storage node with a self-alignment method. Second, the fabrication process can be simpler than the prior fabrication process for the semiconductor memory cell of a noble stacked capacitor cell structure. Third, the storage capacitance of a capacitor can be increased.
    Type: Grant
    Filed: March 12, 1992
    Date of Patent: June 15, 1993
    Assignee: Gold Star Electron Co., Ltd.
    Inventor: Young K. Jun
  • Patent number: 5200367
    Abstract: A method for assembling multilayer packages of semi-conductor elements comprising double molding of the multilayer structure. The method comprises the steps of primarily molding inner leads of a lead frame, secondarily molding the inner leads to form a desired package, and performing in turn die bonding, wire bonding, trimming and forming processes. The double molding process is performed by using an inexpensive molding compound, thereby obtaining packages having a structure equivalent to that of expensive ceramic packages. Accordingly, the manufacture cost of packages is inexpensive and the assembling process is simplified.
    Type: Grant
    Filed: November 6, 1991
    Date of Patent: April 6, 1993
    Assignee: Gold Star Electron Co., Ltd.
    Inventor: Jun S. Ko
  • Patent number: 5182226
    Abstract: The present invention relates to a semiconductor and a method for fabrication thereof and particularly to a semiconductor having a field oxide having a shape such that the lower part is wider that the upper part. Therefore, according to the present invention, the ion implantation process for forming a channel stop region becomes unnecessary, because of the effect of accurate insulation between the devices and the pn junction area can be decreased, so that the junction capacitance becomes decreased. Furthermore, because LOCOS edge does not coincide with the junction edge, the leakage current due to the damage of the edge is not generated. Because a field oxide is of the buried inverse T-type, the effective width of the device is increased more than that of a mask. Because the bird's beak is not generated, the problem due to the narrow width can be settled.
    Type: Grant
    Filed: March 23, 1992
    Date of Patent: January 26, 1993
    Assignee: Gold Star Electron Co., Ltd.
    Inventor: Seong J. Jang
  • Patent number: 5179428
    Abstract: A three-dimensional CCD image sensor comprising a plurality of N type light receiving regions being formed on a two-dimensional plane; a plurality of N type VCCD regions being formed under said plurality of N type light receiving regions; a series of arrangement that said plurality of N type light receiving regions and said plurality of N type VCCD regions are formed opposite to each other being configured in sequence at a desired interval; a desired area of a charge transfer path being formed between each of said plurality of N type light receiving regions and each of said plurality of N type VCCD regions; and a P.sup.+ type charge transfer barrier being formed to a predetermined thickness at the remaining portion except where said charge transfer path is to be formed, between each of said plurality of N type light receiving regions and each of said plurality of N type VCCD regions.
    Type: Grant
    Filed: July 11, 1991
    Date of Patent: January 12, 1993
    Assignee: Gold Star Electron Co., Ltd.
    Inventor: Sung M. Lee
  • Patent number: 5026659
    Abstract: A process for fabricating a stacked trench capacitor of a DRAM by way of the anisotropic dry etch technique of CVD silicon. In the process, sidewalls are formed by the anisotropic dry etch of CVD silicon which is formed within a trench for good electrical isolation between trenches, and upon the wet etch of an oxide film, are served as blocking layers to leave an oxide film layer for isolation in the side surfaces of the trenches. In the bottom part of the trenches in which the oxide film is removed, the ion implantation is performed with dopants having an opposite type in relation to the impurity diffusion area of a transistor for isolating the whole of the trenches effectively. Also, on the slant trench in which sharp edges do not exist the thin dielectric layer is formed to eliminate electrical weakspots.
    Type: Grant
    Filed: June 7, 1990
    Date of Patent: June 25, 1991
    Assignee: Gold Star Electron Co., Ltd.
    Inventor: Young J. Lee