Abstract: An apparatus for controlling data transmissions in a communication network which includes a plurality of nodes connected to a common bus, each of said nodes having a communication processor with a memory and a bus control device associated with the processor.
Type:
Grant
Filed:
October 11, 1995
Date of Patent:
May 27, 1997
Assignee:
GoldStar Information & Communications, Ltd.
Abstract: A wide-area-network (WAN) system and the operation thereof involves a plurality of local-area network (LAN) systems with mobiles, base stations and TRS switching systems, and a systematical WAN system for the TRS switching system having a LAN controller for several LAN systems, thereby controlling wireless transmission signal level, providing communication service even when the mobile moves, and designating the range of communication service available for respective mobile.
Type:
Grant
Filed:
September 7, 1994
Date of Patent:
July 2, 1996
Assignee:
Goldstar Information & Communications, Ltd.
Abstract: A frame stripping method and circuit for judging whether or not of source address matching by comparing the source address of the frame returing after registering the source addresses to CAM chip upon transmitting the frame in FDDI bridge system and transmitting a token with the source addresses within an already registered CAM chip comprise a CAM controller, a CAM sequencer, a plurality of CAM chips, a X bus latch, a CAM data bus generator and a match generator, so that it executes an effective frame stripping and schemes a stabilization of the system operation.
Type:
Grant
Filed:
August 26, 1993
Date of Patent:
October 24, 1995
Assignee:
Goldstar Information & Communication, Ltd.
Abstract: An apparatus for locking a battery cover by which it is convenient to change a battery and by which the battery cover can be firmly locked. The apparatus comprises a body having a hinged portion and an engaged portion in its corner in which a battery housing is formed, a battery cover having a pair of slide pins disposed in the hinged portion of the body in order to be opened and closed, a pair of sliding guide members disposed in the hinged portion of the body in order for the slide pins to be right and left slidably received when she battery cover is opened and closed and a locking knob molded in the engaged portion of the body in order to latch and unlatch the battery cover, the locking knob being upwardly and downwardly movable. As the battery cover can be firmly latched, it is not separated from the body even if accidental impact, vibration or the like is given.
Type:
Grant
Filed:
March 30, 1993
Date of Patent:
December 13, 1994
Assignee:
Goldstar Information & Communications, Ltd.
Abstract: A parallel distributed sample scrambling and descrambling system for fixed-sized packet transmission comprising a parallel scrambler and a parallel descrambler. The scrambler includes; a parallel shift register generator 61 for generating parallel sequences; a sampling means 62 for generating samples from said parallel shift register generator 61; a parallel scrambling means 63 for performing parallel scrambling function by modulo-2 adding the parallel sequences to parallel input data sequences; and a multiplexing means 64.
Type:
Grant
Filed:
March 15, 1993
Date of Patent:
October 11, 1994
Assignees:
Byeong Gi Lee, Seok Chang Kim, Goldstar Information & Communications, Ltd.
Abstract: A distributed sample scrambling system comprising scrambler and a descrambler. The scrambler includes a first shift register generator (SRG) 2 for generating scrambler SRG sequence, an exclusive OR gate 7 for generating a scrambled bitstream by adding the binary sequence to a scrambler input bitstream, and first sampling unit 2 for sampling the scrambler SRG sequence at non-uniform sampling intervals.
Type:
Grant
Filed:
May 22, 1992
Date of Patent:
September 14, 1993
Assignees:
Byeong Gi Lee, Seok Chang Kim, Goldstar Information & Communications Ltd.
Abstract: A parallel scrambling system comprises an M-bit (M>1) interleaved parallel scrambler for parallel scrambling input signals and an M-bit interleaved multiplexer for multiplexing output signals from the M-bit interleaved parallel scrambler. With this arrangement, an M-bit interleaved parallel scrambling of input signals is carried out prior to a multiplexing thereof. The parallel scrambling system also comprises an M-bit interleaved demultiplexer for receiving a parallel scrambled and multiplexed signal from the M-bit interleaved multiplexer and demultiplexing it and an M-bit interleaved parallel descrambler for descrambling output signals from the demultiplexer to make original signals recover. As the scrambling of input signals is carried out prior to the multiplexing thereof, the scrambler can be operated at the rate identical to the transmission rate of input signals, thereby reducing the manufacture cost and electric power consumption to a minimum.
Type:
Grant
Filed:
May 22, 1992
Date of Patent:
August 31, 1993
Assignees:
Byeong Gi Lee, Seok Chang Kim, Goldstar Information & Communications, Ltd.