Abstract: A high speed sampling apparatus based on multiplexed charged coupled devices or sample and hold devices (18) utilises a microprocessor (20) to monitor timing differences between clock signals, each used to clock a respective one of the devices and a reference signal to control a variable timing delay (12, 13, 14) whereby to calibrate each of the devices (18). The control of the variable timing delay (12, 13, 14) is achieved by a digital/analogue converter (15) and additionally, a mark to space ratio control of the variable timing delay is also provided using a digital/analogue converter (16).