Abstract: A digital computer with the capability of incorporating multiple central processing units (CPU's), utilizes an address and data bus between each central processing unit and from one to fifteen intelligent composite memory and input/output modules (MIO). Data is transferred to and from each MIO and the CPU synchronously by a bus during one phase of a three phase clocking cycle. During a second phase of the clocking cycle data on one or more low speed serial data channels within each MIO is transferred to and from the MIO and external devices. During the third phase of the clocking cycle data on a high speed direct memory access channel (DMA) is transferred to and from the MIO and one or more external devices. Additional CPU's can be interconnected with the first CPU by means of an inter-processor buffer module (IPB) which interconnects to the bus at one end and the additional CPU, by means of a bus, at its other end.