Abstract: One embodiment of the present invention performs peripheral operations in a multi-thread processor. A peripheral bus is coupled to a peripheral unit to transfer peripheral information including a command message specifying a peripheral operation. A processing slice is coupled to the peripheral bus to execute a plurality of threads. The plurality of threads includes a first thread sending the command message to the peripheral unit.
Type:
Application
Filed:
March 25, 2009
Publication date:
September 17, 2009
Applicant:
Government Agency - The United States of America as Represented By the Secretary of the Navy
Abstract: One embodiment of the present invention prioritizes resource utilization in a multi-thread processor. A priority register stores thread information for P threads. The thread information includes P priority codes corresponding to the P threads, at least one of the P threads requesting use of at least one resource unit. A priority selector generates assignment signal to assign the at least one resource unit to the at least one of the P threads according to the P priority codes.
Type:
Application
Filed:
April 8, 2009
Publication date:
September 17, 2009
Applicant:
Government Agency - The United States of America as Represented By the Secretary of the Navy