Abstract: An automatic measuring system containing configurable integrated circuits is able to process information via captured images. The automatic measuring system includes a metering instrument, a camera, a recognition module, and a localization module. The metering instrument has at least one display for visually displaying a number and measures the amount of measurable substance or resources (i.e., electricity and water) consumed. The camera captures an image of the number representing at least a portion the amount of measurable substance. The recognition module is operable to generate a value in response to the image and the coordinates wherein the coordinates are used to decode the image via restoring captured image to the original readout counter value. The localization module is removably or remotely coupled to the camera and operable to generate the coordinates in accordance with the image captured by the camera.

Abstract: One embodiment of the present invention discloses a two-phase configuration process (“TCP”) to configure a field-programmable gate array (“FPGA”) to include a configurable microcontroller unit (“CMU”) during a phase I configuration and configuring the CMU during a phase II configuration. TCP, in one aspect, is able to receive first configuration data from a first external storage location via a communication bus. After storing the first configuration data in a first configuration memory for configuring FPGA to contain a CMU for the phase I configuration, second configuration data with MCU attributes is obtained from a second external storage location via the communication bus. The second configuration data is subsequently stored in a second configuration memory for programming the CMU for the phase II configuration.

Abstract: A programmable semiconductor device contains a wireless communication block (“WCB”) capable of facilitating wirelessly field programmable gate array (“FPGA”) programming download as well as functional logic implementation. In one aspect, WCB detects an FPGA access request for initiating an FPGA reconfiguration from a remote system via a wireless communications network. Upon receiving a configuration bitstream for programming the FPGA via the wireless communications network, the configuration bitstream is forwarded from WCB to a configuration download block (“CDB”) for initiating a configuration process. CDB subsequently programs at least a portion of configurable logic blocks (“LBs”) in FPGA in response to the configuration bitstream.

Abstract: A method and/or process of interface bridging device for providing a C physical layer (“C-PHY”) input output interface via a field programmable gate arrays (“FPGA”) is disclosed. The process, in one aspect, is capable of coupling a first wire of data lane 0 to a first terminal of first IO serializer of FPGA for receiving first data from a D-PHY transmitter of a first device and coupling a second wire of the data lane 0 to a second terminal of the first IO serializer of FPGA for receiving second data from the D-PHY transmitter. Upon activating a first scalable low-voltage signal to generate a first value on P channel and a second value on N channel in response to the first data and the second data, a first signal on first wire of trio 0 for a C-PHY output is generated based on the first value on the P channel.

Abstract: An integrated circuit (“IC”) module includes a substrate, multiple field-programmable gate array (“FPGA”) dies, and pads capable of being selectively configured to perform one or more user defined logic functions. The substrate is configured to house multiple FPGA dies side-by-side in an array formation facilitating transmission of signals between the FPGA dies or chips. The FPGA dies are placed on the substrate functioning as a single FPGA device. The periphery dies of the FPGA dies are configured for external connectivity and the interior dies which are interconnected to perform user defined logic functions. The pads, in one aspect, coupling to the FPGA dies, are configured to provide connections between at least some of the FPGA dies.

Abstract: A method for providing a high-speed data communication between a host and field-programmable gate array (“FPGA”) is disclosed. The method, in one embodiment, is capable of identifying a data rate on a bus containing a P-channel and an N-channel operable to transmit signals in accordance with a high-speed Universal Serial Bus (“USB”) protocol. Upon sampling, by a first input deserializer, first two samples of data signals carried by the P-channel in accordance with a first clock signals clocking twice as fast as the data rate of the P-channel, a second input deserializer is used to sample the second two samples of data signals transmitted by the N-channel in accordance with a second clock signal running twice as fast as the data rate of the N-channel with a ninety (90) degree phase shift. The method subsequently forwards the data signals to one or more configurable logic blocks (“LBs”) in FPGA.

Abstract: A system contains a field-programmable gate array (“FPGA”), a controller, and a non-volatile memory (“NVM”) for providing user-defined logic functions. In one aspect, the controller, having a serial peripheral interface (“SPI”) port, is capable of processing information based on execution of instructions. NVM, having a memory SPI port, is configured to store configuration data persistently. FPGA includes multiple configurable logic blocks (“LBs”) configured to be selectively programmed to perform one or more user-defined logic functions in accordance with the configuration data. FPGA, in one embodiment, includes a master SPI (“MSPI”) port which is used to couple to the memory SPI port of NVM and a slave SPI (“SSPI”) port which is used to couple to SPI port of controller.

Abstract: A system containing a host and a device having a field-programmable gate array (“FPGA”) is disclosed. The system includes a set of configurable logic blocks (“LBs”), a bus, and a Universal Serial Bus (“USB”) interface. The configurable LBs, in one aspect, are able to be selectively programmed to perform one or more logic functions. The bus contains a P-channel and an N-channel operable to transmit signals in accordance with a high-speed USB protocol. The USB interface is configured to include a first differential comparator operable to identify a logic zero state at the P-channel and a second differential comparator operable to identify a logic zero state at the N-channel.

Abstract: A programmable integrated circuit (“PIC”) device includes configurable logic blocks (“LBs”), routing connections, and configuration memory for performing user defined programmed logic functions. Each configurable LB, in one example, includes a set of lookup tables (“LUTs”) and associated registers. The LUTs, for example, are configured to generate one or more output signals in accordance with a set of input signals. The registers are arranged so that each register corresponds to one LUT. In one embodiment, a group of registers, instead of assigning to a group of LUTs across multiple configurable LBs, is allocated or configured as embedded signature registers in PSD. For example, a first register which corresponds or physically situated in the vicinity of first LUT can be designated as an embedded signature register for storing a fixed value or signature information for facilitating device or IC identification.

Abstract: A programmable semiconductor system includes a programmable integrated circuit (“PIC”) and storage capable of facilitating a multi-boot with backup default configuration (“MBC”) process. The PIC, in one embodiment, includes configurable logic blocks (“LBs”), routing connections, and a configuration memory for performing logic functions. The storage includes a first and a second memory. While the first memory stores a user configuration data representing user-defined logic functions, the second memory stores a backup default page (“BDP”) containing default configuration data (“DCD”) for programming or booting PIC to its default setting when the user configuration data fails to boot or program PIC. In one aspect, the user configuration data contains the address of the second memory containing DCD.

Abstract: A system contains a field-programmable gate array (“FPGA”), a controller, and a non-volatile memory (“NVM”) for providing user-defined logic functions. In one aspect, the controller, having a serial peripheral interface (“SPI”) port, is capable of processing information based on execution of instructions. NVM, having a memory SPI port, is configured to store configuration data persistently. FPGA includes multiple configurable logic blocks (“LBs”) configured to be selectively programmed to perform one or more user-defined logic functions in accordance with the configuration data. FPGA, in one embodiment, includes a master SPI (“MSPI”) port which is used to couple to the memory SPI port of NVM and a slave SPI (“SSPI”) port which is used to couple to SPI port of controller.

Abstract: A semiconductor device, able to be selectively configured to perform one or more user defined logic functions, includes a semiconductor die and a selectable power regulator. The semiconductor die, in one aspect, includes a first region and a second region. The first region is operatable to perform a first set of logic functions based on a first power domain having a first voltage. The second region is configured to perform a second set of logic functions based on a second power domain having a second voltage. The selectable power regulator, in one embodiment, provides the second voltage for facilitating the second power domain in the second region of the semiconductor die in response to at least one enabling input from the first region of the semiconductor die.

Abstract: A system contains a field-programmable gate array (“FPGA”), a controller, and a non-volatile memory (“NVM”) for providing user-defined logic functions. In one aspect, the controller, having a serial peripheral interface (“SPI”) port, is capable of processing information based on execution of instructions. NVM, having a memory SPI port, is configured to store configuration data persistently. FPGA includes multiple configurable logic blocks (“LBs”) configured to be selectively programmed to perform one or more user-defined logic functions in accordance with the configuration data. FPGA, in one embodiment, includes a master SPI (“MSPI”) port which is used to couple to the memory SPI port of NVM and a slave SPI (“SSPI”) port which is used to couple to SPI port of controller.

Abstract: A programmable integrated circuit device able to be selectively programmed to perform one or more logic functions includes multiple configurable logic blocks (“LBs”), routing fabric, and a nonvolatile memory (“NVM”). While the configurable LBs are able to be selectively programmed to perform one or more logic functions, the routing fabric selectively routes information between the configurable LBs and input/output ports based on a routing configuration signals. The NVM, such as magnetoresistive random access memory (“MRAM”), phase-change memory, or ferroelectric RAM (“FeRAM”), is flexibly organized to contain a configuration NVM storage and a user NVM storage, wherein the user NVM storage is a word addressable memory capable of facilitating random memory access.

Abstract: An automatic measuring system containing configurable integrated circuits is able to process information via captured images. The automatic measuring system includes a metering instrument, a camera, a recognition module, and a localization module. The metering instrument has at least one display for visually displaying a number and measures the amount of measurable substance or resources (i.e., electricity and water) consumed. The camera captures an image of the number representing at least a portion the amount of measurable substance. The recognition module is operable to generate a value in response to the image and the coordinates wherein the coordinates are used to decode the image via restoring captured image to the original readout counter value. The localization module is removably or remotely coupled to the camera and operable to generate the coordinates in accordance with the image captured by the camera.

Abstract: A configurable semiconductor device (“CSD”) is organized in four (4) quadrants able to perform user-defined logic functions via a clock fabric. The first quadrant, in one embodiment, includes a first serializer and deserializer (“SerDes”) region and a bank0 region for data processing. The second quadrant includes a second SerDes region and a bank5 region and the third quadrant contains a bank3 region and a bank4 region. The fourth quadrant includes a bank1 region and a bank2 region. The clock fabric is configured to provide a set of programmable or selectable clock signals with different clock speeds to various regions within the CSD.

Abstract: A programmable semiconductor system includes a programmable integrated circuit (“PIC”) and storage capable of facilitating a multi-boot with backup default configuration (“MBC”) process. The PIC, in one embodiment, includes configurable logic blocks (“LBs”), routing connections, and a configuration memory for performing logic functions. The storage includes a first and a second memory. While the first memory stores a user configuration data representing user-defined logic functions, the second memory stores a backup default page (“BDP”) containing default configuration data (“DCD”) for programming or booting PIC to its default setting when the user configuration data fails to boot or program PIC. In one aspect, the user configuration data contains the address of the second memory containing DCD.

Abstract: A semiconductor device, able to be selectively configured to perform one or more user defined logic functions, includes a semiconductor die and a selectable power regulator. The semiconductor die, in one aspect, includes a first region and a second region. The first region is operatable to perform a first set of logic functions based on a first power domain having a first voltage. The second region is configured to perform a second set of logic functions based on a second power domain having a second voltage. The selectable power regulator, in one embodiment, provides the second voltage for facilitating the second power domain in the second region of the semiconductor die in response to at least one enabling input from the first region of the semiconductor die.

Abstract: A hybrid mode system containing an external device and a field-programmable gate array (“FPGA”) capable of providing configuration data to FPGA via a hybrid communication channel is disclosed. The system is able to identify a first communication protocol in accordance with at least a portion of address bits presented on a serial data line (“SDA”) wherein SDA is used as a connection between FPGA and the external device. The clock signals for receiving data are adjusted to a first clock frequency in accordance with the first communication protocol and clock cycles presented on a serial clock line (“SCL”). SCL is used to connection between FPGA and the external device. After transmitting the configuration data, a portion of FPGA is programmed to perform user-defined logic functions in response to the configuration data.

Abstract: A programmable integrated circuit device able to be selectively programmed to perform one or more logic functions includes multiple configurable logic blocks (“LBs”), routing fabric, and a nonvolatile memory (“NVM”). While the configurable LBs are able to be selectively programmed to perform one or more logic functions, the routing fabric selectively routes information between the configurable LBs and input/output ports based on a routing configuration signals. The NVM, such as magnetoresistive random access memory (“MRAM”), phase-change memory, or ferroelectric RAM (“FeRAM”), is flexibly organized to contain a configuration NVM storage and a user NVM storage, wherein the user NVM storage is a word addressable memory capable of facilitating random memory access.