Abstract: A phase-locked loop circuit receives an input signal that has a predetermined frequency during a succession of symbol intervals and of which the phase during a given symbol interval is related to the phase during a reference interval by the angle 2n.pi./N, where N is a positive integer and n is an integer in the range from 0 to (N-1), and generates a reference signal of which the phase has a desired relationship to the phase of the input signal during the reference interval. The circuit comprises a controllable oscillator that is responsive to a control signal to generate the reference signal, the frequency of the reference signal being equal to the predetermined frequency when the value of the control signal is zero.