Abstract: A system which provides real-time code coverage data on a memory monitored by the system, the code coverage data providing information regarding accesses to the monitored memory, the monitored memory being connected to address lines and data lines, the system comprising: a code coverage memory, the code coverage memory having address inputs and data inputs, wherein signals on the address lines connected to the monitored memory are received at the address inputs of said code coverage memory; and a code coverage control circuit for providing predetermined code coverage data to the data inputs of the code coverage memory. In a preferred embodiment, the code coverage memory is comprised of multiple locations, each of the locations having a predetermined width, and where the code coverage control circuit is adapted to provide predetermined code coverage data in real-time concurrently with the accesses to the monitored memory.
Abstract: A system which provides real-time code coverage data on a memory monitored by the system, the code coverage data providing information regarding accesses to the monitored memory, the monitored memory being connected to address lines and data lines, the system comprising: a code coverage memory, the code coverage memory having address inputs and data inputs, wherein signals on the address lines connected to the monitored memory are received at the address inputs of said code coverage memory; and a code coverage control circuit for providing predetermined code coverage data to the data inputs of the code coverage memory. In a preferred embodiment, the code coverage memory is comprised of multiple locations, each of the locations having a predetermined width, and where the code coverage control circuit is adapted to provide predetermined code coverage data in real-time concurrently with the accesses to the monitored memory.