Patents Assigned to Graphcore Limited
  • Patent number: 11940940
    Abstract: A processing device has a plurality of interfaces and a plurality of processors. During different phases of execution of a computer program, different processors are associated with different interfaces, such that the connectivity between processors and interfaces for the sending of egress data and the receiving of ingress data may change during execution of that computer program. The change in this connectivity is directed by the compiled code running on the processors. The compiled code selects which buses associated with which interfaces, given processors are to connect to for receipt of ingress data. Furthermore, the compiled code causes control messages to be sent to circuitry associated with the interfaces, so as to control which buses associated with which processors, given interfaces are to connect to.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: March 26, 2024
    Assignee: GRAPHCORE LIMITED
    Inventors: Daniel Wilkinson, Stephen Felix, Simon Knowles, Graham Cunningham, David Lacey
  • Patent number: 11928523
    Abstract: A multi-tile processing unit in which the tiles in the processing unit may be divided between two or more different external sync groups for performing barrier synchronisations. In this way, different sets of tiles of the same processing unit each sync with different sets of tiles external to that processing unit.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: March 12, 2024
    Assignee: GRAPHCORE LIMITED
    Inventors: Simon Knowles, Daniel John Pelham Wilkinson, Alan Alexander, Stephen Felix, Richard Osborne, David Lacey, Lars Paul Huse
  • Patent number: 11907628
    Abstract: A computer design verification system comprising a parsing module configured to receive output messages from a computer design testing tool and to compose from the output messages formatted objects comprising a set of fields having field descriptors and test values; a signoff module holding a plurality of signoff objects, each comprising a plurality of fields having a field descriptor, at least some fields populated with a signoff expression, each signoff object associated with a severity level indicative of the severity of a condition represented by the signoff object. The signoff module is configured compare at least one test value in the formatted objects received from the parsing module with at least one signoff expression in the signoff objects to determine if a signoff object matches the formatted object, and in the case of a match, associating the severity level of the signoff object with the formatted object.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: February 20, 2024
    Assignee: GRAPHCORE LIMITED
    Inventors: James Pallister, William Keen, Richard Porter
  • Patent number: 11907725
    Abstract: A computer comprising a plurality of processors, each of which are configured to perform operations on data during a compute phase for the computer and, following a pre-compiled synchronisation barrier, exchange data with at least one other of the processors during an exchange phase for the computer, wherein of the processors in the computer is indexed and the data exchange operations carried out by each processor in the exchange phase depend upon its index value.
    Type: Grant
    Filed: February 3, 2023
    Date of Patent: February 20, 2024
    Assignee: GRAPHCORE LIMITED
    Inventors: Richard Osborne, Matthew Fyles
  • Patent number: 11907772
    Abstract: A device comprising: a processing unit comprising at least one processor configured to: participate in barrier synchronisations, each of which separates a compute phase of the at least one processor from an exchange phase for the at least one processor; and exchange sync messages with a sync controller hardware unit so as to co-ordinate each of the barrier synchronisations; and sync trace circuitry configured to: receive one or more of the sync messages; and in response to each of the one or more of the sync messages, provide sync trace information for output from the device, the sync trace information comprising timing information associated with the respective sync message.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: February 20, 2024
    Assignee: GRAPHCORE LIMITED
    Inventor: Daniel John Pelham Wilkinson
  • Patent number: 11907408
    Abstract: A device comprising a processing unit having a plurality of processors is provided. At least one encryption unit is provided as part of the device for encrypting data written by the processors to external storage and decrypting data read from that storage. The processors are divided into different sets, with state information held in the encryption unit for performing encryption/decryption operations for requests for different sets of processors. This enables interleaved read completions or write requests from different sets of processors to be handled by the encryption unit, since associated state information for each set of processors is independently maintained.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: February 20, 2024
    Assignee: GRAPHCORE LIMITED
    Inventors: Graham Cunningham, Daniel Wilkinson
  • Patent number: 11900109
    Abstract: The present invention relates to an execution unit for executing a computer program comprising a sequence of instructions, which include a masking instruction. The execution unit is configured to execute the masking instruction which, when executed by the execution unit, masks randomly selected values from a source operand of n values and retains other original values from the source operand to generate a result which includes original values from the source operand and symbols in place of the selected values.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: February 13, 2024
    Assignee: GRAPHCORE LIMITED
    Inventors: Stephen Felix, Simon Christian Knowles, Godfrey Da Costa
  • Patent number: 11902149
    Abstract: The provision of redundancy in a sync network, which protects the sync network against faults, such as broken cables in the sync network. The gateway comprises a sync propagation module configured to provide redundant sync requests that are sent along different pathways in the sync network. These sync requests are sent to towards different masters in the sync network. If a fault occurs at a point in one of the paths, the gateway will still receive a sync acknowledgment returned along the other path. Furthermore, the use of redundant sync networks, propagating the sync requests across different paths, allows fault detection in the wiring to be detected.
    Type: Grant
    Filed: November 12, 2021
    Date of Patent: February 13, 2024
    Assignee: GRAPHCORE LIMITED
    Inventor: Lars Paul Huse
  • Patent number: 11893390
    Abstract: A method for debugging a processor which is executing vertices of a software application is described. Each vertex is assigned to a programming thread of the processor. The processor has debug hardware for raising exceptions in certain break conditions. The method comprises inspecting a vertex identifier, comparing the vertex identifier and raising an instruction exception event for the programming thread if the vertex identifier assigned to the thread matches the vertex break identifier in the debug hardware. Exceptions are raised based on identified vertices, rather than just individual instructions or instruction addresses.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: February 6, 2024
    Assignee: GRAPHCORE LIMITED
    Inventors: Alan Graham Alexander, Richard Luke Southwell Osborne, Matthew David Fyles
  • Patent number: 11889615
    Abstract: There is provided a computer structure comprising a first silicon substrate and a second silicon substrate. Computer circuitry configured to perform computing operations is formed in the first silicon substrate, which has a self-supporting depth and an inner facing surface. A plurality of distributed capacitance units are formed in the second silicon substrate, which has an inner facing surface located in overlap with the inner facing surface of the first substrate and is connected to the first substrate via a set of connectors arranged extending depthwise of the structure between the inner facing surfaces. The inner facing surfaces have matching planar surface dimensions. The second substrate has an outer facing surface on which are arranged a plurality of connector terminals for connecting the computer structure to a supply voltage. The second substrate has a smaller depth than the first substrate.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: January 30, 2024
    Assignee: GRAPHCORE LIMITED
    Inventor: Stephen Felix
  • Patent number: 11886982
    Abstract: In a data processing system, at least one processing node is configured to perform computations for a multi-stage process whilst at least one other processor performs the load/unload operations required to calculate a subsequent stage of the multi stage process. An exchange of data then occurs between the processing nodes. At a later time, at least one processing node performs calculations using the data loaded from storage, whilst at least one other processor performs the load/unload operations required to calculate a subsequent stage of the multi stage process.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: January 30, 2024
    Assignee: GRAPHCORE LIMITED
    Inventors: Ola Torudbakken, Lorenzo Cevolani
  • Patent number: 11886505
    Abstract: A function approximation system is disclosed for determining output floating point values of functions calculated using floating point numbers. Complex functions have different shapes in different subsets of their input domain, making them difficult to predict for different values of the input variable. The function approximation system comprises an execution unit configured to determine corresponding values of a given function given a floating point input to the function; a plurality of look up tables for each function type; a correction table of values which determines if corrections to the output value are required; and a table selector for finding an appropriate table for a given function.
    Type: Grant
    Filed: April 5, 2022
    Date of Patent: January 30, 2024
    Assignee: GRAPHCORE LIMITED
    Inventors: Jonathan Mangnall, Stephen Felix
  • Patent number: 11886362
    Abstract: A gateway for use in a computing system to interface a host with the subsystem for acting as a work accelerator to the host, the gateway having an streaming engine for controlling the streaming of batches of data into and out of the gateway in response to pre-compiled data exchange synchronisation points attained by the subsystem, wherein the streaming of batches of data is selectively via at least one of an accelerator interface, a data connection interface, a gateway interface and an memory interface, wherein the streaming engine is configured to perform data preparation processing of the batches of data streamed into the gateway prior to said batches of data being streamed out of the gateway, wherein the data preparation processing comprises at least one of: data augmentation; decompression; and decryption.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: January 30, 2024
    Assignee: GRAPHCORE LIMITED
    Inventors: Ola Torudbakken, Brian Manula
  • Patent number: 11886934
    Abstract: A data processing system comprising a plurality of processing nodes, each comprising at least one memory configured to store an array of data items, wherein each of the plurality of processing nodes is configured to execute compute instructions during a compute phase and following a precompiled synchronisation barrier, enter at least one exchange phase. During the at least one exchange phase, a series of collective operations are carried out. Each processing node is configured to perform a reduce scatter collective in at least one first dimension. Using the results of the reduce scatter collective, each processing node performs an allreduce in a second dimension. The processing nodes then perform an all-gather collective in the at least one first dimension using the results of the allreduce.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: January 30, 2024
    Assignee: GRAPHCORE LIMITED
    Inventors: Lorenzo Cevolani, Fabian Tschopp, Ola Torudbakken
  • Patent number: 11847455
    Abstract: A processing unit having a register file includes: a plurality of registers each having a write enable input configured to receive a write enable signal and a write data input connected to a write data path of the processing unit and configured to write data values from the write data path for storage in a register when the write enable signal is asserted; write circuitry configured in a normal mode of operation to assert the write enable signal of a respective one of the registers to cause operational data values to be written to that register from the write data path; and data cleansing circuitry configured to control a data cleansing mode in which write enable signals of all registers in the register file are simultaneously asserted to cause cleansing data values to be simultaneously written to all registers in the register file from the write data path.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: December 19, 2023
    Assignee: GRAPHCORE LIMITED
    Inventor: Jonathan Louis Ferguson
  • Patent number: 11847428
    Abstract: An execution unit for a processor, the execution unit comprising: a look up table having a plurality of entries, each of the plurality of entries comprising an initial estimate for a result of an operation; a preparatory circuit configured to search the look up table using an index value dependent upon the operand to locate an entry comprising a first initial estimate for a result of the operation; a plurality of processing circuits comprising at least one multiplier circuit; and control circuitry configured to provide the first initial estimate to the at least one multiplier circuit of the plurality of processing circuits so as perform processing, by the plurality of processing units, of the first initial estimate to generate the function result, said processing comprising applying one or more Newton Raphson iterations to the first initial estimate.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: December 19, 2023
    Assignee: GRAPHCORE LIMITED
    Inventors: Jonathan Mangnall, Stephen Felix
  • Patent number: 11841732
    Abstract: A predictive clock controller is provided for modifying the frequency of a clock signal provided to a processing unit based on knowledge of the power usage by the application running on the processing unit during different execution periods. The predictive clock controller counts barrier syncs for the application, so as to determine where the application is in its sync schedule. The predictive clock controller is able to determine from the number of counted syncs, when the application will transition from one execution period to another execution period with different power requirements, and to adjust the clock frequency accordingly.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: December 12, 2023
    Assignee: GRAPHCORE LIMITED
    Inventors: Owain Jones, Daniel John Pelham Wilkinson
  • Patent number: 11822427
    Abstract: Signature generation circuitry is configured to update a signature in response to each of a plurality of writes to memory. The signature is updated by performing bitwise operations between current bit values of the signature and at least some of the bits written to memory in response a write. The bitwise operation are order-independent such that the resulting signature is the same irrespective of the order in which the writes are used to update the signature. The signatures are formed in an order-independent manner such that, if no errors have occurred in generating the data to be written to be memory, the signatures will match. In this way, a compact signature is developed that is suitable export from the data processing device for checking against a corresponding data processing device of a machine running a duplicate application.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: November 21, 2023
    Assignee: GRAPHCORE LIMITED
    Inventors: Stephen Felix, Daniel Wilkinson, Graham Bernard Cunningham
  • Patent number: 11802911
    Abstract: A processor comprises an exchange, a plurality of columns, and a plurality of exchange scan chains. The exchange comprises a plurality of exchange paths, each comprising a set of exchange path portions, for transmitting data between processing units. Each of the plurality of column comprises processing units, each processing unit connected to output data to a respective exchange path, and column pipe circuitry for providing a controllable path between the exchange and the processing units. The column pipe circuitry comprises a column wrapper chain for preventing a scan test signal from passing between the exchange paths and the processing units. The exchange scan chains enable scan testing of the exchange paths. Each exchange scan chain comprises a plurality of scan chain segments, each scan chain segment comprises an exchange path portion connected to at least one of the processing units of at least one of the columns of the processor.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: October 31, 2023
    Assignee: GRAPHCORE LIMITED
    Inventors: Natalie Narkonski, Philip Horsfield
  • Patent number: 11775415
    Abstract: A processor comprising at least one processing module, each processing module comprising: an execution pipeline; memory; an instruction fetch unit comprising operable to switch between an operational mode and a debugging mode, the instruction fetch unit being configured so as, when in the operational mode, to fetch machine code instructions from the memory into the execution pipeline to be executed; and a debug interface for connecting to a debug adapter. The debug interface comprises a debug instruction register enabling the debug adapter to write a machine code instruction to the debug instruction register, and wherein the instruction fetch unit is configured so as, when in the debug mode, to fetch instructions from the debug instruction register into the pipeline instead of from the memory.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: October 3, 2023
    Assignee: GRAPHCORE LIMITED
    Inventors: Alan Graham Alexander, Graham Bernard Cunningham