Patents Assigned to Graphcore Limited
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Patent number: 12164637Abstract: A new apparatus and method for securely distributing an application to processors of a processing unit. The processing unit is formed as part of an integrated circuit and comprises a plurality of processors (referred to as tiles), each having their own execution unit and storage for storing application data and additional executable instructions. The integrated circuit comprises a hardware module (referred to herein as the autoloader) that is configured to distribute a set of bootloader instructions (referred to herein as a secondary bootloader) to each of at least some of the tiles. Each of the tiles then executes instructions of the received secondary bootloader, which causes each tile to issue read requests to read a set of executable application instructions from a memory external to the integrated circuit. Each tile then performs operations using the received set of executable application instructions so as execute the application using the processing unit.Type: GrantFiled: June 4, 2021Date of Patent: December 10, 2024Assignee: GRAPHCORE LIMITEDInventor: Daniel John Pelham Wilkinson
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Patent number: 12140629Abstract: A method for repairing a processor. The processor comprises a plurality of processing units and an exchange comprising a plurality of exchange paths for transmitting data between the processing units. Each processing unit is connected to output data to a respective exchange path. An exchange path functional test of at least a portion of the exchange paths is carried out. Based on the exchange path functional test, it is identified that one or more of the exchange paths is defective, and the processing units connected to the one or more defective exchange paths is identified. The identified processing units are switched out of functional operation of the processor and switching in at least one repair processing unit connected to a non-defective exchange path for functional operation of the processor.Type: GrantFiled: July 22, 2022Date of Patent: November 12, 2024Assignee: GRAPHCORE LIMITEDInventors: Stephen Felix, Natalie Narkonski, Philip Horsfield
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Patent number: 12143244Abstract: A gateway for interfacing a host with a subsystem for acting as a work accelerator to the host. The gateway enables the transfer of batches of data to the subsystem at precompiled data exchange synchronisation points. The gateway acts to route data between accelerators which are connected in a scaled system of multiple gateways and accelerators using a global address space set up at compile time of an application to run on the computer system.Type: GrantFiled: August 30, 2022Date of Patent: November 12, 2024Assignee: GRAPHCORE LIMITEDInventors: Ola Torudbakken, Daniel John Pelham Wilkinson, Brian Manula
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Patent number: 12124892Abstract: Each of the processing devices stores an event vector, which is updated when certain events (e.g. memory errors, overtemperature events) occur on the device. Different elements of the vector correspond to different types of events. When an event of a given type occurs on one device, the update to the event vector on that device is propagated to other devices in the system. Those other devices, in response, update the corresponding element in their own event vector to indicate that an event of that given type has occurred in the system. In this way, events are aggregated between the different devices using the event vector. The event vector is considered to be a global event vector, since its elements indicate whether certain events have occurred across the entire system, and the vector is consistent across the system.Type: GrantFiled: February 28, 2023Date of Patent: October 22, 2024Assignee: GRAPHCORE LIMITEDInventors: Daniel John Pelham Wilkinson, Bjorn Dag Johnsen
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Patent number: 12124699Abstract: A new type of instruction and a control register for the new type of instruction are provided to handle data that may be misaligned in memory. A first part of data (which may be misaligned in memory) is loaded into a first set of registers by loading a first atom containing the first part of data into registers. The pack instruction is executed by an execution unit to place part of data (whose length and starting position are indicated by second and third values in a control register) from one set of registers into an identified location (identified by a first value in the control register) in another set of registers.Type: GrantFiled: November 9, 2022Date of Patent: October 22, 2024Assignee: GRAPHCORE LIMITEDInventors: Alan Alexander, Edward Andrews, Peter Hedinger
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Patent number: 12112164Abstract: A processing device comprising a plurality of operand registers, wherein a first subset of the operand registers are configured to store state information for a plurality of bins, comprising a range of values and a bin count associated with each respective bin, wherein a second subset of the operand registers is configured to store a vector of floating-point values; and an execution unit configured to execute a first instruction taking the state information for the plurality of bins and the vector of floating-point values as operands, and in response to execution of the first instruction, for each of the floating-point values: identify based on an exponent of the respective floating-point value, each one of the plurality of bins for which the respective floating-point value falls within the associated range of values; and increment the bin count associated with the identified bins.Type: GrantFiled: February 28, 2023Date of Patent: October 8, 2024Assignee: GRAPHCORE LIMITEDInventors: Alan Alexander, Simon Knowles, Godfrey Da Costa, Badreddine Noune
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Patent number: 12073262Abstract: A host system compiles a set of local programs which are provided over a network to a plurality of subsystems. By defining the synchronisation activity on the host, and then providing that information to the subsystems, the host can service a large number of subsystems. The defined synchronisation activity includes defining the synchronisation groups between which synchronisation barriers occur and the points during program execution at which data exchange with the host occurs. Defining synchronisation activity between the subsystems allows a large number of subsystems to be connecting whilst minimising the required exchanges with the host.Type: GrantFiled: June 4, 2021Date of Patent: August 27, 2024Assignee: GRAPHCORE LIMITEDInventors: Ola Torudbakken, Wei-Lin Guay
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Patent number: 12056539Abstract: A data processing system comprising a plurality of processing nodes that are arranged to update a model in a parallel manner Each of the processing nodes starts with a different set of updates to model parameters. Each of the processing nodes is configured to perform one or more reduce-scatter collectives so as to exchange and reduce the updates. Having done so, each processing node is configured to apply the reduced set of updates to obtain an updated set of model parameters. The processing nodes then exchange the updated model parameters using an all-gather so that each processing node ends up with the same model parameters at the end of the process.Type: GrantFiled: July 14, 2020Date of Patent: August 6, 2024Assignee: GRAPHCORE LIMITEDInventors: Ola Torudbakken, Lorenzo Cevolani
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Patent number: 12047486Abstract: The device implements a processing pipeline having distinct circuitry for performing encryption/decryption operations and authentication operations and having state stores associated with the respective operations. The state stores store state associated with a given encryption frame, enabling the respective operations to be performed when blocks of data reach that stage in the pipeline. Due to the complexity of operations in a block cipher encryption scheme, the pipeline is deep, which provide the possibility for processing multiple data packets at any one time. The provision of the state stores at the stages in the pipeline at which they are required prevents stalling when a new data packet is received.Type: GrantFiled: June 25, 2021Date of Patent: July 23, 2024Assignee: GRAPHCORE LIMITEDInventor: Graham Cunningham
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Patent number: 12032021Abstract: A method for testing a stacked integrated circuit device comprising a first die and a second die, the method comprising: sending from testing logic of the first die, first testing control signals to first testing apparatus on the first die; in response to the first testing control signals, the first testing apparatus running a first one or more tests for testing functional logic or memory of the first die; sending from the testing logic of the first die, second testing control signals to the second die via through silicon vias formed in a substrate of the first die; and in dependence upon the second testing control signals from the first die, running a second one or more tests for testing the stacked integrated circuit device.Type: GrantFiled: September 22, 2022Date of Patent: July 9, 2024Assignee: Graphcore LimitedInventors: Stephen Felix, Phillip Horsfield
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Patent number: 12019527Abstract: A processor comprises a plurality of processing units, wherein there is a fixed transmission time for transmitting a message from a sending processing unit to a receiving processing unit, based on the physical positions of the sending and receiving processing units in the processor. The processing units are arranged in a column, and the fixed transmission time depends on the position of a processing circuit in the column. An exchange fabric is provided for exchanging messages between sending and receiving processing units, the columns being arranged with respect to the exchange fabric such that the fixed transmission time depends on the distances of the processing circuits with respect to the exchange fabric.Type: GrantFiled: September 10, 2021Date of Patent: June 25, 2024Assignee: Graphcore LimitedInventor: Stephen Felix
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Patent number: 12013781Abstract: For certain applications, parts of the application data held in memory of a processing device (e.g. that are produced as a result of operations performed by the execution unit) are arranged in regular repeating patterns in the memory, and therefore, the execution unit may set up a suitable striding pattern for use by a send engine. The send engine accesses the memory at locations in accordance with the configured striding pattern so as to access a plurality of items of data that are arranged together in a regular pattern. In a similar manner as done for sends, the execution may set up a striding pattern for use by a receive engine. The receive engine, upon receiving a plurality of items of data, causes those items of data to be stored at locations in the memory, as determined in accordance with the configured striding pattern.Type: GrantFiled: March 1, 2022Date of Patent: June 18, 2024Assignee: Graphcore LimitedInventors: Sam Chesney, Alan Graham Alexander, Richard Luke Southwell Osborne, Edward Andrews
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Patent number: 12001263Abstract: There is disclosed a method of controlling the frequency of a clock signal in a processor. The method selects a first clock generator to provide a processor clock signal for executing an application. If a threshold event is detected, a second clock generator is selected. The method reduces the frequency of a clock signal generated by the first clock generator while a processor clock signal is being provided for execution of an application from the second clock generator. The second clock generator generates a clock at a lower speed than the first clock generator. After a predetermined time, the first clock generator is reselected to provide the processor clock signal. The threshold detection is repeated until an optimum clock frequency is discovered.Type: GrantFiled: April 5, 2023Date of Patent: June 4, 2024Assignee: Graphcore LimitedInventors: Stephen Felix, Mrudula Gore
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Patent number: 11966740Abstract: A processor comprising: a register file comprising a group of operand registers for holding data values, each operand register being a fixed number of bits in length for holding a respective data value of that length; and processing logic comprising floating point logic for performing floating point operations on data values in the register file, the floating point logic is configured to process the fixed number of bits in the respective data value according to a floating point format comprising a set of mantissa bits and a set of exponent bits. The processing logic is operable to select between a plurality of different variants of the floating point format, at least some of the variants having a different size sets of mantissa bits and exponent bits relative to one another.Type: GrantFiled: August 10, 2021Date of Patent: April 23, 2024Assignee: Graphcore LimitedInventors: Mrudula Gore, Alan Alexander
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Patent number: 11940940Abstract: A processing device has a plurality of interfaces and a plurality of processors. During different phases of execution of a computer program, different processors are associated with different interfaces, such that the connectivity between processors and interfaces for the sending of egress data and the receiving of ingress data may change during execution of that computer program. The change in this connectivity is directed by the compiled code running on the processors. The compiled code selects which buses associated with which interfaces, given processors are to connect to for receipt of ingress data. Furthermore, the compiled code causes control messages to be sent to circuitry associated with the interfaces, so as to control which buses associated with which processors, given interfaces are to connect to.Type: GrantFiled: April 12, 2022Date of Patent: March 26, 2024Assignee: GRAPHCORE LIMITEDInventors: Daniel Wilkinson, Stephen Felix, Simon Knowles, Graham Cunningham, David Lacey
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Patent number: 11928523Abstract: A multi-tile processing unit in which the tiles in the processing unit may be divided between two or more different external sync groups for performing barrier synchronisations. In this way, different sets of tiles of the same processing unit each sync with different sets of tiles external to that processing unit.Type: GrantFiled: September 1, 2021Date of Patent: March 12, 2024Assignee: GRAPHCORE LIMITEDInventors: Simon Knowles, Daniel John Pelham Wilkinson, Alan Alexander, Stephen Felix, Richard Osborne, David Lacey, Lars Paul Huse
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Patent number: 11907772Abstract: A device comprising: a processing unit comprising at least one processor configured to: participate in barrier synchronisations, each of which separates a compute phase of the at least one processor from an exchange phase for the at least one processor; and exchange sync messages with a sync controller hardware unit so as to co-ordinate each of the barrier synchronisations; and sync trace circuitry configured to: receive one or more of the sync messages; and in response to each of the one or more of the sync messages, provide sync trace information for output from the device, the sync trace information comprising timing information associated with the respective sync message.Type: GrantFiled: August 24, 2021Date of Patent: February 20, 2024Assignee: GRAPHCORE LIMITEDInventor: Daniel John Pelham Wilkinson
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Patent number: 11907725Abstract: A computer comprising a plurality of processors, each of which are configured to perform operations on data during a compute phase for the computer and, following a pre-compiled synchronisation barrier, exchange data with at least one other of the processors during an exchange phase for the computer, wherein of the processors in the computer is indexed and the data exchange operations carried out by each processor in the exchange phase depend upon its index value.Type: GrantFiled: February 3, 2023Date of Patent: February 20, 2024Assignee: GRAPHCORE LIMITEDInventors: Richard Osborne, Matthew Fyles
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Patent number: 11907628Abstract: A computer design verification system comprising a parsing module configured to receive output messages from a computer design testing tool and to compose from the output messages formatted objects comprising a set of fields having field descriptors and test values; a signoff module holding a plurality of signoff objects, each comprising a plurality of fields having a field descriptor, at least some fields populated with a signoff expression, each signoff object associated with a severity level indicative of the severity of a condition represented by the signoff object. The signoff module is configured compare at least one test value in the formatted objects received from the parsing module with at least one signoff expression in the signoff objects to determine if a signoff object matches the formatted object, and in the case of a match, associating the severity level of the signoff object with the formatted object.Type: GrantFiled: May 21, 2021Date of Patent: February 20, 2024Assignee: GRAPHCORE LIMITEDInventors: James Pallister, William Keen, Richard Porter
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Patent number: 11907408Abstract: A device comprising a processing unit having a plurality of processors is provided. At least one encryption unit is provided as part of the device for encrypting data written by the processors to external storage and decrypting data read from that storage. The processors are divided into different sets, with state information held in the encryption unit for performing encryption/decryption operations for requests for different sets of processors. This enables interleaved read completions or write requests from different sets of processors to be handled by the encryption unit, since associated state information for each set of processors is independently maintained.Type: GrantFiled: March 29, 2021Date of Patent: February 20, 2024Assignee: GRAPHCORE LIMITEDInventors: Graham Cunningham, Daniel Wilkinson