Patents Assigned to Graphics Communication Technologies, Ltd.
  • Patent number: 5436626
    Abstract: A variable-length codeword encoder is disclosed which produces 8-bit output segments for storage in a buffer (23) for subsequent transmission over a transmission channel (24). The encoder includes two memory tables (15, 16), which produce in response to each input symbol to be encoded, a variable-length codeword and an a codeword length. An accumulator (31, 33) accumulates, modulo-8, the successive codeword lengths, producing a carry signal during any clock cycle in which eight or more bits codeword bits are accumulated. At each clock cycle, the variable-length codeword is input to the parallel inputs of a cross bar shift control circuit (30). This shift control circuit produces a 16-bit output in which the input word is embedded.
    Type: Grant
    Filed: June 26, 1992
    Date of Patent: July 25, 1995
    Assignees: Bell Communications Research, Inc., Graphics Communication Technologies, Ltd.
    Inventors: Hiroshi Fujiwara, Toshifumi Sakaguchi, Akio Shimatzu, Ming-Ting Sun, Kou-Hu Tzou, Kun-Min Yang
  • Patent number: 5253054
    Abstract: In a moving image encoding apparatus, an image signal is converted into a digital image signal by an A/D converter and is stored in frame memory 110. In addition, a movement vector detector 300 detects a movement of the output of the frame memory 110. In an orthogonal transformer 130, a difference signal between a present frame image which is stored in the frame memory 110 and a previous frame image which is stored in a variable delay frame memory 210 is supplied, in which the difference signal is converted by orthogonal transformation. The orthogonally transformed transformation signal is quantized into a linear or nonlinear discrete level on the basis of a step width of quantization from a step size controller 600 in a quantizer 140. Then, the quantized data is encoded into a variable length code in a variable length encoder 150. A movement vector detector 300 detects movement of the image by pattern matching processing between the present frame and the previous frame.
    Type: Grant
    Filed: August 29, 1991
    Date of Patent: October 12, 1993
    Assignee: Graphics Communication Technologies Ltd.
    Inventors: Hiroshi Fujiwara, Hiroo Uwabu, Masanori Maruyama, Eiji Kakii
  • Patent number: 5241401
    Abstract: An image signal encoding apparatus having a control means for detecting a degree of redundancy of an inputted image signal and for conducting frame skip control based on a frame skip number determination and a determined skip number, an encoding processing means for processing a frame signal indicated by a transmission from said control means by block units into which a screen is divided, quantizing this signal, and encoding and outputting this signal through the medium of a transmission buffer, and a step size control means for controlling the step size of the quantization, characterized in that the step size control means comprises a correction buffer amount calculation means, which calculates a correction buffer amount indicating an excess in the transmission buffer from the frame skip number and a previously supplied transmission speed, and a step size calculation means, which outputs a quantization step size which is smaller as the correction buffer amount indicates a larger excess of the transmission bu
    Type: Grant
    Filed: August 29, 1991
    Date of Patent: August 31, 1993
    Assignee: Graphics Communication Technologies Ltd.
    Inventors: Hiroshi Fujiwara, Hiroo Uwabu, Masanori Maruyama, Eiji Kakii
  • Patent number: 5142361
    Abstract: A motion vector detecting apparatus for detecting motion vectors based on a current frame data and the preceding frame data. In the motion vector detecting apparatus, first and second memories are provided in order to store the current frame data and the preceding frame data. Additionally, a number of first cache memories, a number of second cache memories, a control circuit, and a motion vector calculation circuit are provided. The control circuit selects the input cache memories into which pixel data are to be written, and the output cache memories, from which pixel data are to be read out, from the first and second cache memories, so that the input cache memories and the output cache memories have no redundant cache memory. Pixel data corresponding to the detection image blocks stored in the first memory and pixel data corresponding to the search image blocks stored in the second memory are sequentially written in the selected input cache memories of the first and second cache memories.
    Type: Grant
    Filed: June 19, 1991
    Date of Patent: August 25, 1992
    Assignee: Graphics Communication Technologies, Ltd.
    Inventors: Masashi Tayama, Hiroshi Fujiwara, Masanori Maruyama