Abstract: A system and method for providing a static mode for logic circuits with dynamic latches. The invention provides a reliable static mode for testing of the logic circuit, prevents "through current" power consumption when docks to the logic circuit are stopped, and allows the circuit to be powered down when idle. The system includes a circuit for forcing clock phases to an active state, a circuit for breaking feedback paths within the logic circuit, and an optional clock loss detector for detecting clock inactivity and automatically initiating the static mode.

Abstract: A system and method for providing a static mode for logic circuits with dynamic latches. The invention provides a reliable static mode for testing of the logic circuit, prevents "through current" power consumption when clocks to the logic circuit are stopped, and allows the circuit to be powered down when idle. The system includes a circuit for forcing clock phases to an active state, a circuit for breaking feedback paths within the logic circuit, and an optional clock loss detector for detecting clock inactivity and automatically initiating the static mode.

Abstract: A signal processing system and method for stabilizing cascaded integrator-comb (CIC) interpolation filters. The signal processing system includes an overflow detection circuit and reset circuitry. The overflow detection circuit monitors the output of the CIC interpolation filter for an overflow condition which is indicative of filter instability. When an overflow condition is detected, the reset circuitry automatically resets the filter, thereby eliminating the instability.