Abstract: Technologies relating to efficient memory management for parallel synchronous computing systems are disclosed. Parallel synchronous computing systems may include, for example, a host, a memory management subsystem, and an array of processing units adapted to execute in parallel. Memory management may be implemented at least in part via the memory management subsystem. A memory management subsystem may include one or more memory subsystem layers deployed between the host and the array of processing units. Each memory subsystem layer may have a local memory accessible by entities (whether the host or another layer) above the memory subsystem layer; and a memory controller adapted to manage communications between the entities (whether another layer or the processing units in the array) below the memory subsystem layer.

Abstract: Technologies related to machine transport and execution of logic simulation. In some examples, logic simulation systems may cyclically calculate logic state vectors based on the current state and inputs into the system. The state vector is a state of a logic storage element in a model. State vectors may be distributed from a core of common memory to one or more arrays of processors to compute the next state vector. The one or more arrays of processors are connected with arrays of logic processors and memory for efficiency and speed.

Abstract: A processing architecture and methods are disclosed in which a simulation state vector can be contained in a common memory, formatted in a known form, distributed in a deterministic bus to a sea of logic processors, and returned to the common memory through the deterministic bus.