Patents Assigned to GSI Technology, Inc.
  • Patent number: 12259859
    Abstract: A deduplication system includes a similarity searcher, a difference calculator, and a storage manager. The similarity searcher searches for a similar fingerprint in a database storing a plurality of local sensitive fingerprints, resembling a new fingerprint of a new block. The difference calculator computes a difference block between the input block and a similar block associated with the found similar fingerprint, and the storage manager updates the database with the new fingerprint and stores the difference block, if not empty, in a store. A method for deduplication includes searching in a database, storing a plurality of local sensitive fingerprints, a similar fingerprint, resembling a new fingerprint of a new block, calculating a difference block between the input block and a similar block associated with the similar fingerprint, if found, updating the database with the new fingerprint and storing the difference block, if it is not empty, in a storage unit.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: March 25, 2025
    Assignee: GSI Technology Inc.
    Inventors: Avidan Akerib, Dan Ilan, Eli Ehrman, Elona Erez
  • Patent number: 12210539
    Abstract: A method for selecting items one by one from a set of items elected from a large dataset of items includes determining whether or not a density of the set is sparse. If the density is sparse, the method includes repeatedly performing an extreme item select (EIS) method to select a next one of the elected items from the set and removing the next one from the set to create a next set. If the density is not sparse, the method includes performing a next index select (NIS) method to create a linked list of the elected items and to repeatedly select a next elected item from the set.
    Type: Grant
    Filed: December 17, 2023
    Date of Patent: January 28, 2025
    Assignee: GSI Technology Inc.
    Inventors: Moshe Lazer, Eli Ehrman
  • Patent number: 12210537
    Abstract: A similarity search system includes a database of original vectors, a hierarchical database of bins and a similarity searcher. The hierarchical database of bins is stored in an associative memory array, each bin identified by an order vector representing at least one original vector and the dimension of the order vector is smaller than the dimension of the original vector. The similarity searcher searches in the database for at least one similar bin whose order vector resembles an order vector representing a query vector and provides at least one original vector represented by the bin resembling the query vector.
    Type: Grant
    Filed: April 26, 2020
    Date of Patent: January 28, 2025
    Assignee: GSI Technology Inc.
    Inventors: Dan Ilan, Amir Gottlieb
  • Patent number: 12159123
    Abstract: A method to compare between a first number and a second number includes the steps of storing the first number in a first row of an associative memory array, storing a two's complement representation of the second number in a second row of the associative memory array wherein bit i of the second number is stored in a same column of the associative memory array as bit i of the first number, concurrently performing a carry save operation on a plurality of columns of the associative memory array to create a sum and a carry, predicting a value of a carry out bit without adding the sum and the carry, and indicating that the first number is smaller than the second number if the value of the carry out bit is 1.
    Type: Grant
    Filed: December 17, 2023
    Date of Patent: December 3, 2024
    Assignee: GSI Technology Inc.
    Inventor: Dan Ilan
  • Patent number: 12135725
    Abstract: A system for measuring similarity between a binary query vector and a plurality of binary candidate vectors includes a storage unit and a processor. The storage unit stores the binary query vector and the plurality of candidate vectors, and the processor performs Tanimoto calculations in terms of Hamming distances.
    Type: Grant
    Filed: May 4, 2023
    Date of Patent: November 5, 2024
    Assignee: GSI Technology Inc.
    Inventor: Samuel Lifsches
  • Patent number: 12131779
    Abstract: A memory device includes a plurality of memory units and a global responder (RSP) unit. Each memory unit includes a memory array of memory cells arranged in rows and columns, and an RSP unit. The memory array receives horizontal input data rotated for storage as data candidates in columns of the array. At least one of the rows is a calculation row receiving per-bit-line Boolean AND operations between bits of a marker row and bits of a row of data of the data candidates. The RSP unit includes wired-OR circuitry operative on the calculation row to generate a responder signal indicating whether there is one cell in the calculation row having a predefined value identifying a data candidate in the memory array. The global RSP unit receives multiple responder signals, one from at least two of the RSP units, and performs Boolean OR operations on the multiple responder signals.
    Type: Grant
    Filed: June 5, 2023
    Date of Patent: October 29, 2024
    Assignee: GSI Technology Inc.
    Inventors: Avidan Akerib, Eli Ehrman
  • Patent number: 12106071
    Abstract: A method for calculating a square root B having N bits of a number X having 2N bits includes iterating on bits bi of square root B starting from the most significant bit until the least significant bit of square root B. For each iteration, the method includes locating a 1 at the squared location of bit bi in a CHECK variable, determining the value of bit bi from the result of a comparison of number X with a function of all previously found bits and a previous comparison outcome, shifting all previously found bits right 1 location in a CHECK variable, and adding the determined value of bit bi into its squared location in the CHECK variable.
    Type: Grant
    Filed: January 5, 2023
    Date of Patent: October 1, 2024
    Assignee: GSI Technology Inc.
    Inventors: Eyal Amiel, Moshe Lazer, Samuel Lifsches
  • Patent number: 12079478
    Abstract: A method for random data distribution in a memory array from a source row to a destination row includes receiving a plurality of pairs of addresses, where each pair includes a source address of a source cell in the source row and a destination addresses of a destination cell in a destination row, storing the source address in cells of a column associated with the destination cell, creating a Boolean algebra expression defining a correlation between each one of the source addresses and a value stored in each one of the source cells, where applying the Boolean algebra expression on any one of the source addresses provides a value of one of the source cells, concurrently applying the Boolean algebra expression on a plurality of columns storing the source addresses and concurrently writing a plurality of results on the destination row.
    Type: Grant
    Filed: December 19, 2022
    Date of Patent: September 3, 2024
    Assignee: GSI Technology Inc.
    Inventor: Avidan Akerib
  • Patent number: 12073328
    Abstract: A method for machine learning includes extracting features from a training set of inputs, wherein each input generates a feature set and each the feature set forms a neural network key. The method includes arranging the keys in an in-memory computational layer such that the distance between any pair of keys corresponding to similar inputs is as close as possible while keys for a pair of dissimilar inputs have differing values as far apart as possible, wherein each of the keys has a fixed size. The method also includes searching through the dataset using an in-memory K-nearest neighbor unit to find K keys similar to a query key, the searching occurring in a constant amount of time as a function of the fixed size and irrespective of a size of the dataset.
    Type: Grant
    Filed: August 5, 2018
    Date of Patent: August 27, 2024
    Assignee: GSI Technology Inc.
    Inventor: Eli Ehrman
  • Patent number: 12050885
    Abstract: A method for binary division includes the steps of having a current remainder provided as a sum bit-vector and a carry bit-vector, performing a carry save add operation between the sum bit-vector and the carry bit-vector and a two's complement representation of a denominator to produce a temporary sum and a temporary carry, predicting a sign bit of a full total of the temporary sum and the temporary carry and updating the remainder with the temporary sum and the temporary carry and incrementing a quotient if the sign bit is 0.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: July 30, 2024
    Assignee: GSI Technology Inc.
    Inventor: Dan Ilan
  • Patent number: 12027238
    Abstract: A protein searcher includes a pre-trained CNN, a feature extractor, a database and a KNN searcher. The pre-trained CNN, trained on a previously classified amino acid database, receives an unidentified amino acid sequence. The feature extractor extracts a feature vector of the unidentified amino acid sequence as a query feature vector. The database stores feature vectors of trained amino acid sequences and of at least one untrained amino acid sequence and stores associated classes of the trained amino acid sequences and associated tags of the at least one untrained amino acid sequence. The KNN searcher finds K feature vectors of the database which are close to the query feature vector and outputs the associated class or tag of each of the K feature vectors.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: July 2, 2024
    Assignee: GSI Technology Inc.
    Inventor: Elona Erez
  • Patent number: 12008068
    Abstract: A device for in memory vector-matrix multiplication includes a memory array and in-memory logic. The memory array has at least two sections and stores a multiplier matrix. The memory array also receives and stores an input multiplicand arranged in a vector such that the operands of the vector-matrix multiplication are located on a same column of the memory array. Each of the sections is one of: a volatile memory array, a non-volatile memory array, a destructive memory array and a non-destructive memory array. The in-memory logic computes an output of the vector-matrix multiplication using the stored input vector and the stored multiplier matrix. The memory array is one of the following type of memory array: RAM, DRAM, SRAM, Re-RAM, ZRAM, MRAM and Memristor.
    Type: Grant
    Filed: July 19, 2023
    Date of Patent: June 11, 2024
    Assignee: GSI Technology Inc.
    Inventors: Avidan Akerib, Pat Lasserre
  • Patent number: 11991290
    Abstract: A system to dynamically calculate a root hash value from a plurality of leaf hash values includes a flat associative memory and a hash parser. The flat associative memory stores a plurality of leaf hash values. The hash parser extracts a compressed number of branch nodes from the plurality of leaf hash values, determines branch node relationships from the plurality of leaf hash values, and saves the compressed number of branch nodes, and the branch node relationships.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: May 21, 2024
    Assignee: GSI Technology Inc.
    Inventor: Dan Ilan
  • Patent number: 11989185
    Abstract: A cascading search system includes an associative memory array, a similarity match processor and an exact match processor. The columns of the array store a plurality of multiportion data vectors and have a first section, for a first portion of a vector, a second section for storing a second portion of a vector and a match row. The similarity match processor performs a parallel similarity search of a similarity query in the first sections and stores a match bit indication in the match row of the column. Each match bit indication indicates if its column has a first portion which matches the similarity query. The exact match processor performs an exact search in parallel in the second section of each similarity matched column whose match bit indication indicates a match of its first section and outputs those similarity matched columns whose second portions match the exact query.
    Type: Grant
    Filed: December 1, 2022
    Date of Patent: May 21, 2024
    Assignee: GSI Technology Inc.
    Inventor: Avidan Akerib
  • Patent number: 11941407
    Abstract: A unit for accumulating a plurality N of multiplied M bit values includes a receiving unit, a bit-wise multiplier and a bit-wise accumulator. The receiving unit receives a pipeline of multiplicands A and B such that, at each cycle, a new set of multiplicands is received. The bit-wise multiplier bit-wise multiplies bits of a current multiplicand A with bits of a current multiplicand B and to sum and carry between bit-wise multipliers. The bit-wise accumulator accumulates output of the bit-wise multiplier thereby to accumulate the multiplicands during the pipelining process.
    Type: Grant
    Filed: April 5, 2020
    Date of Patent: March 26, 2024
    Assignee: GSI Technology Inc.
    Inventor: Avidan Akerib
  • Patent number: 11860885
    Abstract: An associative memory array includes a plurality of associative memory cells arranged in rows and columns where each first cell in a first row and in a first column has access to a content of a second cell in a second row in an adjacent column.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: January 2, 2024
    Assignee: GSI Technology Inc.
    Inventors: Moshe Lazer, Eli Ehrman
  • Patent number: 11763881
    Abstract: A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function. The memory cell may have a read port in which the digital data stored in the storage cell of the memory cell is isolated from the read bit line.
    Type: Grant
    Filed: April 2, 2021
    Date of Patent: September 19, 2023
    Assignee: GSI Technology, Inc.
    Inventors: Lee-Lean Shu, Eli Ehrman
  • Patent number: 11763136
    Abstract: A system for training a neural-network-based floating-point-to-binary feature vector encoder preserves the locality relationships between samples in an input space over to an output space. The system includes a neural network under training and a probability distribution loss function generator. The neural network has floating-point inputs and floating-point pseudo-bipolar outputs. The generator compares an input probability distribution constructed from floating-point cosine similarities of an input space and an output probability distribution constructed from floating-point pseudo-bipolar pseudo-Hamming similarities of an output space. The system includes a proxy vector set generator to take a random sampling of vectors from training data for a proxy set, a sample vector selector to select sample vectors from the training data and a KNN vector set generator to find a set of k nearest neighbors closest to each sample vector from said proxy set for a reference set.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: September 19, 2023
    Assignee: GSI Technology Inc.
    Inventor: Daphna Idelson
  • Patent number: 11755240
    Abstract: A method for an associative memory device includes storing a plurality of pairs of multi-bit operands X and Y in rows of a memory array of the associative memory device, each pair in a different column of the memory array. Cells in a column are connected by a first bit-line providing a value of activated cells and a second bit-line providing an inverse value of the activated cells. The bits of X are stored in first rows and the bits of Y are stored in second rows. The method includes reading an inverse value of a bit stored in each of the second rows using the second bit-line, writing it to third rows and concurrently, on all columns, performing multi-bit add operations between a value of X, an inverse value of Y and a carry-in bit initiated to 1, providing the difference between X and Y in each of the columns.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: September 12, 2023
    Assignee: GSI Technology Inc.
    Inventors: Moshe Lazer, Eyal Amiel
  • Patent number: 11734385
    Abstract: A method for in memory computation of a neural network, the neural network having weights arranged in a matrix, includes previously storing the matrix in an associated memory device, receiving an input arranged in a vector and storing it in the memory device, and in-memory, computing an output of the network using the input and the weights.
    Type: Grant
    Filed: March 7, 2021
    Date of Patent: August 22, 2023
    Assignee: GSI Technology Inc.
    Inventors: Avidan Akerib, Pat Lasserre