Patents Assigned to GSI Technology, Inc.
  • Patent number: 10425070
    Abstract: Systems and methods associated with reducing clock skew are disclosed. In some exemplary embodiments, there is provided circuitry associated with lock loop circuits such as a phase lock loop (PLL). Such circuitry may comprise output clock tree circuitry and phase averaging circuitry. In other exemplary embodiments, there is provided circuitry associated with delay lock loop (DLL) circuits. Such circuitry may comprise output clock tree circuitry and/or phase averaging circuitry.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: September 24, 2019
    Assignee: GSI Technology, Inc.
    Inventors: Yu-Chi Cheng, Patrick Chuang, Jae-Hyeong Kim
  • Patent number: 10402165
    Abstract: A system includes a non-destructive associative memory array and a predictor, a selector and a summer. The memory array includes a plurality of sections, each section includes cells arranged in rows and columns, to store bit j from a first multi-bit number and bit j from a second multi-bit number in a same column in section j. The predictor generally concurrently predicts a plurality of carry out values in each of the sections and the selector selects one of the predicted carry out values for all bits. The summer generally concurrently, for all bits, calculates a sum of the multi-bit numbers using the selected carry-out values.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: September 3, 2019
    Assignee: GSI Technology Inc.
    Inventor: Moshe Lazer
  • Patent number: 10303629
    Abstract: Systems, methods and fabrication processes relating to memory devices involving data bus inversion are disclosed. According to one illustrative implementation, a memory device may comprise a memory core, circuitry that receives a data bus inversion (OBI) bit associated with a data signal as input directly, without transmission through OBI logic associated with an input buffer, and circuitry that stores the OBI bit into the memory core, reads the OBI bit from the memory core, and provides the OBI bit as output. In further implementations, memory devices herein may store and process the OBI bit on an internal data bus as a regular data bit.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: May 28, 2019
    Assignee: GSI TECHNOLOGY, INC.
    Inventor: Lee-Lean Shu
  • Patent number: 10249362
    Abstract: A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function. The memory cell may have a read port in which the digital data stored in the storage cell of the memory cell is isolated from the read bit line.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: April 2, 2019
    Assignee: GSI Technology, Inc.
    Inventors: Lee-Lean Shu, Eli Ehrman
  • Patent number: 10210935
    Abstract: A multiple instruction, multiple data memory device includes a memory array with several sections, one or more multiplexers between the sections and a decoder. Each section has memory cells arranged in rows and columns. The cells in a row are connected by a read enabled word line and by a write enabled word line. The decoder includes a decoder memory array which generally simultaneously activates a plurality of read enabled word lines in several sections, a plurality of write enabled word lines in several sections and one or more multiplexers. The decoder memory array includes several bit lines oriented perpendicularly to and connected to the rows of the memory array. A method of activating in-memory computation using several bit lines of a decoder memory array, connected to rows of the memory array to simultaneously activate several read enabled word lines, several write enabled word lines and one or more multiplexers.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: February 19, 2019
    Assignee: GSI Technology Inc.
    Inventors: Avidan Akerib, Eli Ehrman
  • Patent number: 10192592
    Abstract: Systems, methods and fabrication processes relating to dynamic random access memory (DRAM) devices involving data signals grouped into 10 bits are disclosed. According to one illustrative implementation a DRAM device may comprise a memory core, circuitry that receives a data bus inversion (DBI) bit associated with a data signal as input directly, without transmission through DBI logic associated with an input buffer, circuitry that stores the DBI bit into the memory core, reads the DBI bit from the memory core, and provides the DBI bit as output. In further implementations, DRAM devices herein may store and process the DBI bit on an internal data bus as a regular data bit.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: January 29, 2019
    Assignee: GSI TECHNOLOGY, INC.
    Inventors: Lee-Lean Shu, Paul M. Chiang, Soon-Kyu Park, Gi-Won Cha
  • Patent number: 10153042
    Abstract: A computing device includes bit line processors, multiplexers and a decoder. Each bit line processor includes a bit line of memory cells and each cell stores one bit of a data word. A column of bit line processors stores the bits of the data word. Each multiplexer connects a bit line processor in a first row of bit line processors to a bit line processor in a second row of bit line processors. The decoder activates at least two word lines of the bit line processor of the first row and a word line in the bit line processor in the second row and enables a bit line voltage associated with a result of a logical operation performed by the bit line processor in the first row to be written into the cell in the bit line processor in the second row.
    Type: Grant
    Filed: July 16, 2017
    Date of Patent: December 11, 2018
    Assignee: GSI Technology Inc.
    Inventors: Eli Ehrman, Avidan Akerib
  • Patent number: 9966118
    Abstract: Systems and methods of synchronous memories and synchronous memory operation are disclosed. According to one illustrative implementation, a memory device is disclosed comprising memory circuitry having a memory output, the memory circuitry including a sense amplifier having a first output and a second output, a first data path coupled to the first output of the sense amplifier, the first data path including 2 latches/registers, and a second data path coupled to the second output of the sense amplifier, the second data path including a plurality latches/registers. In further implementations, various control circuitry, connections and control signals may be utilized to operate the latches/registers in the first and second data paths according to specified configurations, control, modes, latency and/or timing domain information, to achieve, for example, pipelined output latching and/or double data rate output.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: May 8, 2018
    Assignee: GSI Technology, Inc.
    Inventors: Lee-Lean Shu, Yoshinori Sato
  • Patent number: 9935635
    Abstract: A system may include a first inverter configured to invert a first data signal and a second inverter configured to invert a second data signal. A pull-up element may be coupled to an output of the first inverter on a first terminal and a power source on a second terminal, wherein the power source is also coupled to a pull-up element of a main output buffer. A pull-down element may be coupled to an output of the second inverter on a first terminal and a ground on a second terminal, wherein the ground is also coupled to a pull-down element of the main output buffer.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: April 3, 2018
    Assignee: GSI Technology, Inc.
    Inventors: Jae-Hyeong Kim, Chih Tseng, Patrick Chuang
  • Patent number: 9859902
    Abstract: Systems and methods are disclosed relating to fields of clock/data acquisition or handling, such as clock/data locking and the like. In one exemplary implementation, phase lock loop (PLL) circuitry may comprise voltage controlled oscillator (VCO) circuitry, phase frequency detector, converting circuitry, and frequency detector (FD) circuitry that outputs a frequency difference signal proportional to frequency difference between frequencies of a feedback clock signal and a reference clock signal.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: January 2, 2018
    Assignee: GSI Technology, Inc.
    Inventor: Chao-Hung Chang
  • Patent number: 9859005
    Abstract: Disclosed is a method of selecting a data candidate having a maximum value from a plurality of data candidates stored in columns in a memory array. The method includes computing marker bit values for each row of data in the memory array, and performing a Boolean OR operation on the marker bit values to generate a responder signal value. Also disclosed is a memory device including a memory array of memory cells arranged in rows and columns, and responder signal circuitry to generate a responder signal responsive to positive identification of a data candidate in the memory array.
    Type: Grant
    Filed: January 12, 2015
    Date of Patent: January 2, 2018
    Assignee: GSI Technology Inc.
    Inventors: Avidan Akerib, Eli Ehrman
  • Patent number: 9853633
    Abstract: Systems and methods associated with reducing clock skew are disclosed. In some exemplary embodiments, there is provided circuitry associated with lock loop circuits such as a phase lock loop (PLL). Such circuitry may comprise output clock tree circuitry and phase averaging circuitry. In other exemplary embodiments, there is provided circuitry associated with delay lock loop (DLL) circuits. Such circuitry may comprise output clock tree circuitry and/or phase averaging circuitry.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: December 26, 2017
    Assignee: GSI TECHNOLOGY, INC.
    Inventors: Yu-Chi Cheng, Patrick Chuang, Jae-Hyeong Kim
  • Patent number: 9853634
    Abstract: Systems and methods associated with phase frequency detection are disclosed. In one illustrative implementation, a phase frequency detection (PFD) circuit device may comprise first circuitry and second circuitry having a set input, a reset input, and an output, wherein the set input has a higher priority than the reset input, and additional circuitry arranged and operatively coupled to provide advantageous operation of the PFD circuit device. According to some implementations, for example, systems and methods with clock edge overriding reset features, extended detection range(s), and/or reduction of reverse charge after cycle slipping are provided.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: December 26, 2017
    Assignee: GSI Technology, Inc.
    Inventor: Chao-Hung Chang
  • Patent number: 9847111
    Abstract: Systems and methods of synchronous memories and synchronous memory operation are disclosed. According to one illustrative implementation, a memory device is disclosed comprising memory circuitry having a memory output, the memory circuitry including a sense amplifier having a first output and a second output, a first data path coupled to the first output of the sense amplifier, the first data path including 2 latches/registers, and a second data path coupled to the second output of the sense amplifier, the second data path including a plurality latches/registers. In further implementations, various control circuitry, connections and control signals may be utilized to operate the latches/registers in the first and second data paths according to specified configurations, control, modes, latency and/or timing domain information, to achieve, for example, pipelined output latching and/or double data rate output.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: December 19, 2017
    Assignee: GSI TECHNOLOGY, INC.
    Inventors: Lee-Lean Shu, Yoshinori Sato
  • Patent number: 9804856
    Abstract: A method of operating a clock frequency detected control I/O buffer enable circuitry and/or features of saving power. In illustrative implementations, the method may be directed to providing low standby power consumption, such as providing low standby power consumption in high-speed synchronous SRAM and RLDRAM devices.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: October 31, 2017
    Assignee: GSI Technology, Inc.
    Inventors: Young-Nam Oh, Soon Kyu Park, Jae Hyeong Kim
  • Patent number: 9729159
    Abstract: Systems and methods involving phase-locked-loop (PLL) circuitry are disclosed. In one illustrative implementation, a PLL circuit device may comprise voltage controlled oscillator (VCO) circuitry having a bias signal that sets a frequency range, circuitry that shifts the VCO circuitry to operate in one of the frequency ranges, and other circuitry to compare/calibrate signals and/or set the bias current. According to further implementations, as a function of operation of the circuitry, an operating frequency range of the VCO circuitry may be shifted to a different operating frequency range, and closed-loop, continuous frequency range, auto-calibration or other features may be provided.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: August 8, 2017
    Assignee: GSI Technology, Inc.
    Inventor: Yu-Chi Cheng
  • Patent number: 9722618
    Abstract: Systems and methods involving phase-locked-loop (PLL) circuitry are disclosed. In one illustrative implementation, a PLL circuit device may comprise voltage controlled oscillator (VCO) circuitry having a bias signal that sets a frequency range, circuitry that shifts the VCO circuitry to operate in one of the frequency ranges, and other circuitry to compare/calibrate signals and/or set the bias current. According to further implementations, as a function of operation of the circuitry, an operating frequency range of the VCO circuitry may be shifted to a different operating frequency range, and closed-loop, continuous frequency range, auto-calibration or other features may be provided.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: August 1, 2017
    Assignee: GSI TECHNOLOGY, INC.
    Inventor: Yu-Chi Cheng
  • Patent number: 9692429
    Abstract: Systems and methods are disclosed relating to fields of clock/data acquisition or handling, such as clock/data locking and the like. In one exemplary implementation, phase lock loop (PLL) circuitry may comprise voltage controlled oscillator (VCO) circuitry, phase frequency detector, converting circuitry, and frequency detector (FD) circuitry that outputs a frequency difference signal proportional to frequency difference between frequencies of a feedback clock signal and a reference clock signal.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: June 27, 2017
    Assignee: GSI Technology, Inc.
    Inventor: Chao-Hung Chang
  • Patent number: 9679631
    Abstract: Systems and methods are disclosed for increasing the performance of static random access memory (SRAM). Various systems herein, for example, may include or involve dual- or multi-pipe, multi-bank SRAMs, such as Quad-B2 SRAMs. In one illustrative implementation, there is provided an SRAM memory device including a memory array comprising a plurality of SRAM banks and pairs of separate and distinct pipes associated with each of the SRAM banks, wherein each pair of pipes may provide independent access to its associated SRAM bank.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: June 13, 2017
    Assignee: GSI Technology, Inc.
    Inventors: Robert Haig, Patrick Chuang, Chih Tseng, Mu-Hsiang Huang
  • Patent number: 9653166
    Abstract: A computing device includes a memory array built of several sections having memory cells arranged in rows and column, at least one cell in each column of the memory array being connected to a bit line; and at least one multiplexer to connect a bit line in a first column of a first section to a bit line in a second column in a second section different from the first section, where the second column is not continuous with the first column ; and a decoder to activate at least two word lines of the first section and a word line connected to a cell in the second column in the second section to write a bit line voltage associated with a result of a logical operation performed on the first column into the cell in the second column.
    Type: Grant
    Filed: July 10, 2016
    Date of Patent: May 16, 2017
    Assignee: GSI Technology Inc.
    Inventors: Avidan Akerib, Eli Ehrman