Patents Assigned to GSI Technology, Inc.
  • Computational memory cell and processing array device using the memory cells for XOR and XNOR computations
    Patent number: 11763881
    Abstract: A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function. The memory cell may have a read port in which the digital data stored in the storage cell of the memory cell is isolated from the read bit line.
    Type: Grant
    Filed: April 2, 2021
    Date of Patent: September 19, 2023
    Assignee: GSI Technology, Inc.
    Inventors: Lee-Lean Shu, Eli Ehrman
  • Orthogonal data transposition system and method during data transfers to/from a processing array
    Patent number: 11409528
    Abstract: A device and method for facilitating orthogonal data transposition during data transfers to/from a processing array and a storage memory since the data words processed by the processing array (using computational memory cells) are stored orthogonally to how the data words are stored in storage memory. Thus, when data words are transferred between storage memory and the processing array, a mechanism orthogonally transposes the data words.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: August 9, 2022
    Assignee: GSI Technology, Inc.
    Inventors: Bob Haig, Patrick Chuang, Chih Tseng, Mu-Hsiang Huang
  • Write data processing methods associated with computational memory cells
    Patent number: 11257540
    Abstract: A write data processing method associated with computational memory cells formed as a memory/processing array provides the ability to shift data between adjacent bit lines in each section of the memory/processing array or the same relative bit lines in adjacent sections of the memory/processing array.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: February 22, 2022
    Assignee: GSI Technology, Inc.
    Inventors: Bob Haig, Eli Ehrman, Chao-Hung Chang, Mu-Hsiang Huang
  • Storage array circuits and methods for computational memory cells
    Patent number: 11227653
    Abstract: A storage array for computational memory cells formed as a memory/processing array provides storage of the data without using the more complicated computational memory cells for storage. The storage array may have multiple columns of the storage cells coupled to a column of the computational memory cells. The storage array may have ECC circuitry.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: January 18, 2022
    Assignee: GSI Technology, inc.
    Inventors: Lee-Lean Shu, Park Soon-Kyu, Paul M. Chiang
  • Read data processing circuits and methods associated with computational memory cells
    Patent number: 11205476
    Abstract: A read register is provided that captures and stores the read result on a read bit line connected to a set of computational memory cells. The read register may be implemented in the set of computational memory cell to enable the logical XOR, logical AND, and/or logical OR accumulation of read results in the read register. The set of computational memory cells with the read register provides a mechanism for performing complex logical functions across multiple computational memory cells connected to the same read bit line.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: December 21, 2021
    Assignee: GSI TECHNOLOGY, INC.
    Inventors: Bob Haig, Eli Ehrman, Chao-Hung Chang, Mu-Hsiang Huang
  • Results processing circuits and methods associated with computational memory cells
    Patent number: 11194519
    Abstract: A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array (having a plurality of bit line sections) provides a mechanism to logically combine the computation results across multiple bit line sections in a section and across multiple sections, and transmit the combined result as an output of the processing array and/or store the combined result into one or more of those multiple bit line sections.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: December 7, 2021
    Assignee: GSI TECHNOLOGY, INC.
    Inventors: Bob Haig, Eli Ehrman, Dan Ilan, Patrick Chuang, Chao-Hung Chang, Mu-Hsiang Huang
  • Processing array device that performs one cycle full adder operation and bit line read/write logic features
    Patent number: 11194548
    Abstract: A processing array that performs one cycle full adder operations. The processing array may have different bit line read/write logic that permits different operations to be performed.
    Type: Grant
    Filed: October 6, 2020
    Date of Patent: December 7, 2021
    Assignee: GSI Technology, Inc.
    Inventors: Lee-Lean Shu, Bob Haig, Chao-Hung Chang
  • Computational memory cell and processing array device using memory cells
    Patent number: 11150903
    Abstract: A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean AND, a boolean OR, a boolean NAND or a boolean NOR. The memory cell may have a read port that has isolation circuits that isolate the data stored in the storage cell of the memory cell from the read bit line.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: October 19, 2021
    Assignee: GSI TECHNOLOGY, INC.
    Inventors: Lee-Lean Shu, Chao-Hung Chang, Avidan Akerib
  • Write data processing circuits and methods associated with computational memory cells
    Patent number: 11094374
    Abstract: A write data processing apparatus and method associated with computational memory cells formed as a memory/processing array provides the ability to shift data between adjacent bit lines in each section of the memory/processing array or the same relative bit lines in adjacent sections of the memory/processing array. The memory/processing array has one or more sections and each section has its own unique set of “n” bit lines.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: August 17, 2021
    Assignee: GSI TECHNOLOGY, INC.
    Inventors: Bob Haig, Eli Ehrman, Chao-Hung Chang, Mu-Hsiang Huang
  • COMPUTATIONAL MEMORY CELL AND PROCESSING ARRAY DEVICE USING THE MEMORY CELLS FOR XOR AND XNOR COMPUTATIONS
    Publication number: 20210225436
    Abstract: A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function. The memory cell may have a read port in which the digital data stored in the storage cell of the memory cell is isolated from the read bit line.
    Type: Application
    Filed: April 2, 2021
    Publication date: July 22, 2021
    Applicant: GSI Technology, Inc.
    Inventors: Lee-Lean Shu, Eli Ehrman
  • COMPUTATIONAL MEMORY CELL AND PROCESSING ARRAY DEVICE USING THE MEMORY CELLS FOR XOR AND XNOR COMPUTATIONS
    Publication number: 20210225437
    Abstract: A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function. The memory cell may have a read port in which the digital data stored in the storage cell of the memory cell is isolated from the read bit line.
    Type: Application
    Filed: April 2, 2021
    Publication date: July 22, 2021
    Applicant: GSI Technology, Inc.
    Inventors: Lee-Lean Shu, Eli Ehrman
  • RESULTS PROCESSING CIRCUITS AND METHODS ASSOCIATED WITH COMPUTATIONAL MEMORY CELLS
    Publication number: 20210216246
    Abstract: A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array (having a plurality of bit line sections) provides a mechanism to logically combine the computation results across multiple bit line sections in a section and across multiple sections, and transmit the combined result as an output of the processing array and/or store the combined result into one or more of those multiple bit line sections.
    Type: Application
    Filed: October 27, 2020
    Publication date: July 15, 2021
    Applicant: GSI Technology, Inc.
    Inventors: Bob HAIG, Eli EHRMAN, Dan ILAN, Patrick CHUANG, Chao-Hung CHANG, Mu-Hsiang HUANG
  • ORTHOGONAL DATA TRANSPOSITION SYSTEM AND METHOD DURING DATA TRANSFERS TO/FROM A PROCESSING ARRAY
    Publication number: 20210173647
    Abstract: A device and method for facilitating orthogonal data transposition during data transfers to/from a processing array and a storage memory since the data words processed by the processing array (using computational memory cells) are stored orthogonally to how the data words are stored in storage memory. Thus, when data words are transferred between storage memory and the processing array, a mechanism orthogonally transposes the data words.
    Type: Application
    Filed: October 28, 2020
    Publication date: June 10, 2021
    Applicant: GSI Technology, Inc.
    Inventors: Bob HAIG, Patrick CHUANG, Chih TSENG, Mu-Hsiang HUANG
  • Computational memory cell and processing array device using the memory cells for XOR and XNOR computations
    Patent number: 10998040
    Abstract: A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function. The memory cell may have a read port in which the digital data stored in the storage cell of the memory cell is isolated from the read bit line.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: May 4, 2021
    Assignee: GSI TECHNOLOGY, INC.
    Inventors: Lee-Lean Shu, Eli Ehrman
  • Computational memory cell and processing array device using complementary exclusive or memory cells
    Patent number: 10958272
    Abstract: A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function. The memory cell may have a read port in which the digital data stored in the storage cell of the memory cell is isolated from the read bit line.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: March 23, 2021
    Assignee: GSI Technology, Inc.
    Inventors: Lee-Lean Shu, Avidan Akerib
  • Ultra low VDD memory cell with ratioless write port
    Patent number: 10943648
    Abstract: An ultra low VDD memory cell has a ratioless write port. In some embodiments, the VDD operation level can be as low as the threshold voltage of NMOS and PMOS transistors of the cell.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: March 9, 2021
    Assignee: GSI Technology, Inc.
    Inventors: Lee-Lean Shu, Patrick Chuang, Chao-Hung Chang
  • Processing array device that performs one cycle full adder operation and bit line read/write logic features
    Patent number: 10930341
    Abstract: A processing array that performs one cycle full adder operations. The processing array may have different bit line read/write logic that permits different operations to be performed.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: February 23, 2021
    Assignee: GSI Technology, Inc.
    Inventors: Lee-Lean Shu, Bob Haig, Chao-Hung Chang
  • PROCESSING ARRAY DEVICE THAT PERFORMS ONE CYCLE FULL ADDER OPERATION AND BIT LINE READ/WRITE LOGIC FEATURES
    Publication number: 20210027815
    Abstract: A processing array that performs one cycle full adder operations. The processing array may have different bit line read/write logic that permits different operations to be performed.
    Type: Application
    Filed: October 6, 2020
    Publication date: January 28, 2021
    Applicant: GSI Technology, Inc.
    Inventors: Lee-Lean SHU, Bob HAIG, Chao-Hung CHANG
  • WRITE DATA PROCESSING METHODS ASSOCIATED WITH COMPUTATIONAL MEMORY CELLS
    Publication number: 20210027834
    Abstract: A write data processing method associated with computational memory cells formed as a memory/processing array provides the ability to shift data between adjacent bit lines in each section of the memory/processing array or the same relative bit lines in adjacent sections of the memory/processing array.
    Type: Application
    Filed: October 9, 2020
    Publication date: January 28, 2021
    Applicant: GSI Technology, Inc.
    Inventors: Bob Haig, Eli Ehrman, Chao-Hung Chang, Mu-Hsiang Huang
  • Results processing circuits and methods associated with computational memory cells
    Patent number: 10891076
    Abstract: A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array (having a plurality of bit line sections) provides a mechanism to logically combine the computation results across multiple bit line sections in a section and across multiple sections, and transmit the combined result as an output of the processing array and/or store the combined result into one or more of those multiple bit line sections.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: January 12, 2021
    Assignee: GSI Technology, Inc.
    Inventors: Bob Haig, Eli Ehrman, Dan Ilan, Patrick Chuang, Chao-Hung Chang, Mu-Hsiang Huang