Abstract: The disclosure relates to a control means for converting serially transmitted di-phase data bits into parallel data bits having corresponding discrete logic levels. The control means of the present invention is adapted for use in a di-phase pulse receiving system of the type which includes a positive peak detector for providing a first pulse upon detecting a positive di-phase signal portion and a negative peak detector for providing a second pulse upon detecting a negative di-phase signal portion.

Abstract: A control device is described for linking a motor operated data terminal to a data processor which provides information signals including data characters and data terminal motor-start signals. The motor associated with the data terminal is selectively operable between an on condition and an off condition and is programmed to switch from the on condition to the off condition after a first predetermined interval following the last reception of data characters from the data processor. The data terminal motor switches to the on condition upon receipt of a data terminal motor-start signal and reaches its normal operating speed in at least a second predetermined interval after the receipt of a data terminal motor-start signal. The control device includes means for receiving the information signals from the data processor and for transmitting such signals to the data terminal.

Abstract: A register and sender module with an internal common control provided with common addressing, storage, and timing for up to four registers, up to two senders, and up to two tone control circuits in a module. Modular construction allows addition and replacement of the various circuits in the module on an as required basis with a minimum of rewiring. An internal bus couples all module circuits to the internal common control. Each register and sender in the module is accessible from every inlet to the module. Provision is made for single digit storage to the registers and senders and single digit read out from the sender.

Abstract: The disclosure relates to a balanced tone application system for applying dial tones, busy tones, or the like generated by a tone generator, to telephone transmission line pairs in a balanced manner and for use in a telephone exchange of the type having a supervisory relay coupled across an associated transmission line pair. The system comprises a transformer having a primary coupled to the tone generator and a secondary including first and second windings, a power source coupled to the first winding, a source of common potential coupled to the second winding, and a switching means coupled to the first winding, the second winding, the power source, the source of common potential, and to the supervisory relay.

Abstract: A sense amplifier having three transistor stages. A balanced differential input stage with high noise immunity to capacitively coupled noise. A second threshold stage is provided with protection against an output being caused by a permanent potential on the input, false trigger protection circuitry, and protection against supply voltage and other minor variations. A differential output stage increases noise immunity of the amplifier output and protects against a short circuit in the output.

Abstract: An active hybrid circuit for providing isolation between a signal receiving line and a signal transmitting line coupled to a two-wire telephone subset. The receiving line is coupled to a receiving amplifier having a differential output coupled to a pair of common terminals. The telephone subset is also connected to the two common terminals. The two common terminals are connected to the two inputs of a transmitting operational amplifier. The transmitting signal line is coupled to the output of the transmitting amplifier. A compensating network is connected between the input to the receiving amplifier and one of the inputs to the transmitting amplifier.

Abstract: A central processor for controlling the operation of the subsystems of a telephone exchange switching system which are interconnected on a common data bus to establish requested service between telephone subscribers, wherein the exchange system includes a program memory also connected to the common data bus for storing a plurality of selectable multiple bit operational codes to be utilized by the central processor in response to a particular service being requested, a program address register for selecting a desired operational code from the program memory, an instruction register for storing the selected operational codes and a control word generator which provides function control signals in response to the particular operational codes stored in the instruction register. A bit time counter coupled to the control word generator controls the timing of the central processor so that the function control signals are supplied in proper time sequence.

Abstract: A TCMF and MF decoder with common decoder section and separate TCMF and MF control sections. The decoder is time shared between two or more registers served on a first-come, first-served basis with priority assigned to one in case of identical seizure time. Strapping options are provided to allow the two registers to be both TCMF registers, or both MF registers, or one of each.

Abstract: A dial pulse receiver having a clock pulse input to a counter and a first and second flip-flop. The outputs of the two flip-flops are coupled to an exclusive OR gate to reset the counter. The counter output and the two outputs of the second flip-flop are coupled to an output gate and latch configuration. The counter is set to enable the latches so only a legitimate dial pulse is recorded.

Abstract: A side of line detector with a single operational amplifier with adjustable output. The amplifier input is protected from positive and negative voltage spikes by diodes. Two transistors are coupled to the amplifier to set a comparator voltage reference which allows the rejection of leakage and noise. Test points are provided in the circuit to facilitate testing particular subcircuits and to allow the initial adjustment of the detector.

Abstract: A shift register is provided with two inputs and two outputs. One input is from a free running clock and a second input is provided for relay operate and release signals. The two outputs are coupled to a NAND gate to provide a longer relay operate than release time. The two outputs are coupled to a NOR gate for a longer relay release time than operate time. Either gate output is coupled to a relay driver to operate the relay.