Abstract: A dynamic RAM refresh circuit provides the interface for timely refresh of up to 64K of RAM memory while simultaneously providing for minimal disruption of a CPU's access of that RAM memory. Circuitry is also provided to permit interlock control for timeshared access of the RAM memory on a shared basis with the refresh circuit.
Abstract: A speech synthesized answering circuit for use with a telepone subscriber station. A microprocessor control circuit monitors a telephone line for detection of a predetermined number of ringing signal bursts. A read-only-memory contains a vocabulary of digitized words. The microprocessor answers the line and forms a telephone answering message by retrieving selected digitized words from the read-only-memory. This message is transferred to a speech processor which converts it to analog format and couples it onto the calling telephone line.
Abstract: The present invention provides for synchronizing signals transmitted to two duplex copies of hardware from a common source. Signals sent from the source to the duplex copies of hardware may arrive asynchronously at the two copies and require synchronization. In addition, the duplex hardware may be validly operated in the simplex mode of operation, which requires no synchronization of the two hardware copies.
Abstract: An apparatus for controlling the charge rate and voltage of storage batteries of a solar power generating system using a single voltage regulator module to monitor and control the state of charge of any number of cells of a battery and a number of solar modules.
Abstract: In a PCM telecommunications switching system, an arrangement for deriving a clock signal from incoming PCM data of a digital span is shown. This derived clock signal is synchronized and continuously locked to the incoming PCM data of the digital span. The present digital phase locking arrangement cyclically adjusts the derive clock signal so that on the average synchronism is maintained.
Abstract: This circuit provides for synchronizing the internal clocks of at least two central processing unit process controllers. In order to synchronize the internal clocks of these central processing units (CPUs), the CPUs periodically execute a predetermined set of operating instructions which cause their internal clocks to coincide. This synchronization function is dynamic in that it is continually performed in an on-line fashion while the processors are performing their telecommunication process control function.
Abstract: An address sequencer and memory arrangement is shown for transferring data in the form of message bytes to and from a plurality of digital data links. The address sequencer and memory arrangement includes a memory circuit having a plurality of memory location areas associated with each of the plurality of digital data links. A counter circuit connected to the memory circuit is loaded with a preset count by a link processor complex. The counter increments and outputs to the memory circuit addresses which sequentially access each of the memory location areas, transferring each message byte to a data link output buffer for transmission over a respective one of the plurality of digital data links. Alternatively, the counter addresses sequentially each memory location area transferring a message byte to each memory location area from each of the plurality of digital data links via a data link input buffer.
Abstract: A switching isolated single transistor forward converter which performs demagnetization and snubbing functions with the same network. The transformer stored energy and the energy stored during snubbing are transferred to the load by the network during the dead time of the switching cycle.
Abstract: A two amplifier subscriber line interface circuit that uses a novel voltage divider technique for providing power to the two lower voltage amplifiers from a 50 volt central office battery. This is achieved by using one lower power amplifier with a Zener regulator diode in shunt thereof to regulate its current.
Abstract: An alarm apparatus for use with a numerically controlled twisted pair wire wrap wiring machine that indicates to the operator the position and the wire of a pair that is to be wired. The apparatus is connected to the indicator lights of the machine and to the wiring gun to sense the gun placement on the pin. The proper conditions are logically combined, should a condition be changed as by placing a signal wire on a grounded pin an alarm is sounded.
Abstract: The present invention is an interconnection of a loop analysis test system (LATS) to a digital switching system. This arrangement includes the utilization of existing network units to establish a path connection from the computer of a LATS system to a measuring unit of the LATS system. This path through the digital switching system provides for the appropriate signaling requirements in order to simulate a telephone call to the digital switching system for connection to a subscriber. Another path is provided to connect the measuring unit to the subscriber line to be tested via a special access network. In addition, this arrangement includes a data base in the CPU switching system to provide for determining whether the connection of this path through the switching system is for a test access or for normal calling functions. The data base also records the interconnection of equipment such that the proper subscriber's line may be accessed when called by the LATS system.
Abstract: A cross-copy arrangement is shown for synchronizing parity clock signals in a duplex digital system. Each copy of the duplex system generates a local timing signal and a remote timing signal. The remote signal of each copy is crossed over and logically combined with the local timing signal generating a parity clock signal.
Abstract: The present invention is an interconnection of a loop analysis test system (LATS) to a digital switching system. This arrangement includes the utilization of existing network units to establish a path connection from the computer of a LATS system to a measuring unit of the LATS system. This path through the digital switching system provides for the appropriate signaling requirements in order to simulate a telephone call to the digital switching system for connection to a subscriber. In addition, this arrangement includes a data base in the CPU switching system to provide for determining whether the connection of this path through the switching system is for a test access or for normal calling functions. The data base also records the interconnection of equipment such that the proper subscriber's line may be accessed when called by the LATS system.
Abstract: A speech synthesized time announcement circuit for use with a telephone line control circuit. Upon detection of a predetermined number of ringing signal bursts or a predetermined keypad provided data pattern or a predetermined time period, a control microprocessor determines the current time of day and forms a time-of-day message by retrieving selected digitized words from a read-only memory. This message is transferred to a speech processor which converts it to analog format. If the time of day request was received over a telephone line, the control microprocessor causes the speech processor to answer the line and couple the time-of-day message onto the line. If the request was received by internal interrupt or via the keypad, the control processor causes the speech microprocessor to announce the message locally by applying it to a local speaker.
Abstract: A circuit which eliminates race conditions caused by gate delay variation. In the absence of gate delay variations data is made available for a period of time which extends beyond commencement of processing of such data. This circuit prevents gate delay variations from causing processing to commence after the period of time during which data is available. Each of a pair of flip-flops initiates or terminates the data available time period. These flip-flops, an exclusive-or gate and related circuitry are arranged such that the period of time for data availability is not terminated until after processing of such data actually commences.
Abstract: A memory access selection circuit including a microprocessor, address, data and control multiplexers, a random access memory, storage circuits and related logic circuitry. This circuit allows both an external processor and the microprocessor to receive data from and transmit data to, the random access memory. The microprocessor controls access of the external processor to the random access memory by controlling and monitoring the multiplexer and storage circuits. This prevents erroneous data, address and control signals from appearing at the memory when switching between the microprocessor and the external processor as sources to the memory.
Abstract: A method and apparatus for limiting the interference caused by shadows of minute particles of opaque matter that settles on the surface of an assembly of a metal substrate, a resist and an overlay by placing a second glass overlay on top of the assembly to raise the surface to a level where the shadows of any particles resting there will be diffused.
December 21, 1983
Date of Patent:
September 3, 1985
GTE Automatic Electric Incorporated
Richard Jarocinski, William R. Keaton, Joseph L. Magennis
Abstract: A clock selection circuit which selects and enables one of a plurality of clock circuits in response to initialization by a processing unit or detection of failure of an on-line clock circuit. The clock circuits are selected on the basis of a priority arrangement. The clock circuit failure is detected by a retriggerable monostable multivibrator and the selection priority is based on time delays generated by programmed counters associated with each clock circuit.
Abstract: A double file printed wiring board module arranged to mount printed wiring boards on both sides of a centrally positioned interconnect or side plane while providing for the convection cooling of the printed wiring boards and the interconnection of same with conductors of minimal length. The printed wiring boards are supported by a connector at one side edge and a board guide at an opposite side edge. The interconnect or side plane includes an external termination connector mounted at its rear edge to permit the efficient connection of the circuit module to external terminations.
Abstract: A tool for facilitating the insertion of miniature cable connectors into mating receptacles from both top and bottom. The bottom includes guide arms to maintain the contact pins in proper alignment until entry into a mating receptacle is made.
December 19, 1983
Date of Patent:
August 20, 1985
GTE Automatic Electric Incorporated
James J. Grammas, Walter J. Moskal, Craig J. Witt