Abstract: A time-space-time switching network is shown in which there is a multiple crossover of voice information from one rail to another rail in a large digital switching system. The time and control unit is divided into two rails both incoming and outgoing. Each rail multiplexes two 193 channel streams into one 386 channel stream of information. These two rails crossover in either or both the originating and terminating time switching stages but remain segregated throughout the space switching stage.

Abstract: A method of determining splice loss 10 log (1-P.sub.R /P.sub.O) that is practiced at the location of a splice between one ends of input and output fibers. A reference level P.sub.O of light that is transmitted out of the one end of the input fiber is obtained by inserting it into an integrating cylinder of split block construction, prior to making the splice, and coupling diffuse light in the cylinder to a radiometer. After the ends of the fibers are spliced together, the splice and a significant portion of the adjacent length of output fiber exhibiting substantial leaky mode radiation that is caused by the splice, is located in the cylinder. With light of the reference level in the input fiber being incident on the splice, the radiometer provides an indication P.sub.R of light lost as a result of the splice. The indication P.sub.

Abstract: One or a burst of error signals from an error detector are applied to one input of a latch. The first error received during a "window" forces the latch to a set position, and a subsequent enabling pulse reads the error occurrence into the count up input of an up-down counter. Following the enable pulse, the latch is reset. If one or more errors occur during the subsequent window period, another error occurrence is read into the count up input. Otherwise, the occurrence of the enable pulse reads the absence of an error into the down count input of said up-down counter. On a full count, an output latch circuit is set by an output signal from the counter. The latch is not reset until a zero count is obtained in the up-down counter. Overflow and underflow are prohibited by circuits external to the up-down counter.

Abstract: A circuit for simulating the parallel combination of a floating inductor and capacitor in the bilinear and LDI domains has a pair of nodes receiving an input voltage and connected to input terminals of associated first and second voltage followers. A first capacitor C1 is alternately or periodically connected across the output terminals of the voltage followers for sampling the input voltage, and connected between the output of the second voltage follower and the input terminal of an integrator including a second capacitor C2 which integrates and stores the charge voltage on C1. A third capacitor is periodically connected to the nodes for sampling the input voltage, and connected between the output terminals of the first voltage follower and the integrator for subsequently also sampling and storing the integrated voltage on C2. The sum of the input voltage and the integrated voltage that is stored by C3 is discharged to the new input voltage when C3 is again connected across the nodes.

Abstract: A control circuit 16 that is responsive to voltage conditions on a cable pair transmission line for selectively disabling a battey charging circuit 12 operating off of line current comprises a resistor R5 and storage capacitor C2 connected in series across the line; a timing capacitor C1 connected between the cathode of a PUT (programmable unijunction transistor) and one wire 32 of the line; and a zener diode D1 between the PUT anode and one wire 32 for establishing a conduction threshold for the PUT. The resistor R5 and primary conduction path of a first bipolar transistor Q2, having its base connected to the PUT anode, are connected in series between the other wire 33 of the line and the charging circuit so that startup current for the charging circuit may be used for charging C2 when the charging circuit is disabled. Means is also included for driving the PUT gate voltage low and turning on the PUT in response to both high and low voltage conditions on the line.

Abstract: An integratable circuit that simulates a source resistor comprises first and second nodes for connection to a voltage source and a virtual ground, respectively; a first integrated capacitor C1; and switch means operative for alternately electrically connecting C1's top and bottom plates to the first node and ground, respectively, and to ground and the second node, respectively, during first and second non-overlapping time periods in each time interval T for charging C1 to the source voltage and discharging C1 into the second node, respectively, where T is the time interval between adjacent second time periods and f=1/T is the switching frequency for C1.

Abstract: A control circuit 16 that is responsive to voltage conditions on a cable pair transmission line for selectively disabling a battery charging circuit 12 operating off of line current comprises a resistor R5 and storage capacitor C2 connected in series across the line; a timing capacitor C1 connected between the cathode of a PUT (programmable unijunction transistor) and one wire 32 of the line; and a zener diode D1 between the PUT anode and one wire 32 for establishing a conduction threshold for the PUT. The resistor R5 and primary conduction path of a first bipolar transistor Q2, having its base connected to the PUT anode, are connected in series between the other wire 33 of the line and the charging circuit so that startup current for the charging circuit may be used for charging C2 when the charging circuit is disabled. Means is also included for driving the PUT gate voltage low and turning on the PUT in response to both high and low voltage conditions on the line.

Abstract: A small amount of light that is transmitted in one of a pair of optical fibers having cleaved ends thereof loosely brought into butt contact is converted to leaky modes in the other fiber. Leaky mode light that is radiated out of the perimeter of the other fiber is collected in an integrating enclosure located proximate its one end and extending over a limited length of the other fiber. The light in the enclosure is detected for producing a measure of the degree of alignment of the adjacent ends of the fibers. After the cleaved ends of the fibers are aligned with micromanipulators so as to null the intensity of detected leaky mode radiation, an electrical arc is created across them for permanently joining the fiber ends together in a splice. The integrity of the resultant splice is determined by producing a measure of the splice loss 10 log (1-P.sub.R /P.sub.O), where P.sub.

Abstract: An integrated circuit comprising first and second nodes that are connected to external circuitry, a voltage follower having input and output terminals electrically connected between the second node and the bottom plate of a first integrated capacitor C1, and second and third integrated capacitors C2 and C3 having the bottom plates thereof connected to a ground reference potential. A switch means is operative for periodically electrically connecting the top plate of C1 to the first and second nodes during first and second non-overlapping time periods in each time interval T for discharging C1 and charging C1 to the difference voltage across the nodes, respectively, where T is the time interval between adjacent second time periods and f=1/T is the switching frequency for C1. The switch means also operates for periodically electrically connecting the top plates of C2 and C3 to the second and first nodes.

Abstract: First and second NPN transistors are direct connected in an astable multivibrator configuration. Each collector is connected to the positive terminal of a DC power source through series connected diodes. A resistor, which is selected to control the amplitude of oscillation, is connected between the collectors. The frequency of oscillation is controlled by a frequency determining component which is connected between the emitters of said transistors. The emitters are connected to current sources.

Abstract: In an amplifier station for a trunk system, switching apparatus responsive to the absence or presence of a control signal selectively passes R. F. signals in a prescribed frequency band on a main transmission line to first and second lines. During normal operation of the amplifier relay coils are energized so as to engage second and third contacts for passing signals on the second line with amplification. When the amplifier is operating properly, PIN diodes short opposite ends of the first line for improving isolation in the station equipment. In the event of amplifier malfunction, first and third contacts are engaged thereby providing transmission along the first line. A tubular conductive member surrounds the switch contacts so as to provide capacitive coupling thereto. The tubular member is capacitively coupled to a ground plane to thereby by-pass signals which are above the desired passband of the trunk system.

Abstract: This simulation circuit is a one-port network having a pair of nodes connected to inputs of first and second voltage followers that have associated switched capacitors alternately connected across them for being discharged and connected to an integrator for being charged to the output voltage on the latter. A third switched capacitor is alternately connected in series with the voltage follower outputs for sensing the input voltage applied to the nodes, and connected to the integrator where the input voltage is integrated and transferred to the first and second switched capacitors. A floating inductance L=T.sup.2 C4/C1C3 is simulated across the nodes, where T is the reciprocal of the switching frequency, C1, C2 and C3 are the capacitances of associated switched capacitors, C1=C2, C4 is the capacitance in the integrator, and the circuit is characterized by the LDI transformation.

Abstract: An integratable switched capacitor simulation circuit comprising an integrated capacitor C3 having bottom and top plates thereof electrically connected to first and second nodes, and a pair of integrated capacitors C1 and C2 having their top plates electrically connected together. The bottom plate of C2 is electrically connected to the output of a voltage follower that has its input terminal connected to the second node. A first switch means periodically connects the top plates of C1 and C2 to the first and second nodes at a prescribed rate. When the first node is connected to a voltage source and the bottom plate of C1 is connected to either ground or the first node, the circuit simulates a source resistor across the nodes. When the first node and bottom plate of C1 are connected to ground, the circuit simulates a grounded resistor. In alternate embodiments, the capacitances of C1 and/or C3 may be zero valued for presenting an open circuit across the terminals thereof.

Abstract: Sinusoidal timing reference signals, each of which is associated with a different suppresed-sync scrambled-priority television channel signal, frequency modulate associated carrier frequency signals for producing modulated carrier signals that are combined with a continuous wave (CW) sinusoidal carrier frequency signal. After low-pass filtering to block harmonic frequencies that may interfere with the video carriers of composite television signals, only the fundamentals of the CW and modulated carrier signals are combined with non-scrambled and/or scrambled composite television signals for transmission to subscriber's equipment. In a descrambler at a subscriber location, the CW carrier signal is mixed with the modulated carrier signals to produce frequency modulated IF signals containing timing information for associated priority television channel signals.

Abstract: An inverter accepts the true form of a high-frequency signal at its input and provides the complement thereof at its output. The true form is applied to a first input of a first NAND-gate and the complementary form is applied to a first input of a second NAND-gate. A second signal, having a repetition rate which is set, for example, by the channel spacing required in an FDM carrier system, is applied to the second inputs of said first and second NAND-gates. The second signal is thereby alternately switched between the first and second output terminals of said NAND-gates at a rate equal to the frequency of the high-frequency signal. The first and second output terminals of said NAND-gates are connected to the first and second end terminals, respectively, of the primary winding of an output transformer. The end terminals of the secondary winding of said transformer are connected to the load or utilization device. The output signal comprises a spectrum having a sin x/x envelope centered at the high-frequency w.

Abstract: During scribing of a ceramic plate with a laser beam, ceramic particles rise from the workpiece in a direction of motion that is generally the same as that of the workpiece. The lens on a laser scriber is protected from abrasive contact with such particulates in the atmosphere by slipping the base of a housing over the circumference of the lens mount and forming a generally airtight seal between them. The housing is shaped like a frustum of a right circular cone, with the apex end thereof truncated and essentially rolled over to form an orifice through which the lens axis and laser beam pass. A plurality of streams of pressurized air are introduced into the housing near the midpoint of the frustum and the lens surface. The air streams are introduced tangent to the inner surface of the housing and angled downward for producing a vortex of air that is exhausted to the atmosphere through the orifice at a velocity and vorticity that inhibits particulates outside of the cover entering the orifice.

Abstract: Paste solder is contact printed onto lead and component pads of a leaded hybrid substrate through holes that are arranged in a plate in the pattern of the pads, a first recess in the solder or top side of the plate extending over the area containing component holes. In order to accommodate lead frames of single in-line packages (SIP), a second recess is formed in the bottom or substrate side of the plate adjacent lead holes that are defined by a plate thickness that is slightly greater than the height of lead tines located on lead pads. In a printing operation, the bottom of the plate is moved into contact with the padded side of the substrate of a SIP, with lead tines on lead pads being located in associated lead holes and the lead frame in the second recess. Paste solder is then squeegeed over the top of the plate for printing solder onto the component and lead pads of the substrate in a single printing operation.

Abstract: The base electrode of the switching transistor in a converter is resistively connected to the output terminal of a pulse width modulator and connected through first and second series connected diodes to a ground reference potential which is also connected to the emitter of the transistor, the junction between the diodes being electrically connected through a large capacitor to the modulator output terminal. Voltage pulses at the output terminal cause the transistor to pass collector current and the second diode to conduct for charging the capacitor. On termination of voltage pulses, the modulator connects the output terminal thereof to ground. This causes the charge voltage on the capacitor to turn the first diode on to pull the base voltage sharply negative for rapidly drawing minority carriers out of the base region.

Abstract: During scribing of a ceramic plate with a laser beam, ceramic particles rise from the workpiece in a direction of motion that is generally the same as that of the workpiece. The lens on a laser scriber is protected from abrasive contact with such particulates in the atmosphere by slipping the base of a housing over the circumference of the lens mount and forming a generally airtight seal between them. The housing is shaped like a frustum of a right circular cone, with the apex end thereof truncated and essentially rolled over to form an orifice through which the lens axis and laser beam pass. A plurality of streams of pressurized air are introduced into the housing near the midpoint of the frustum and the lens surface. The air streams are introduced tangent to the inner surface of the housing and angled downward for producing a vortex of air that is exhausted to the atmosphere through the orifice at a velocity and vorticity that inhibits particulates outside of the cover entering the orifice.

Abstract: A two terminal circuit comprising a capacitive element (with a negative capacitance of value -C/2) connected between the terminals, and an integrated capacitor (with a positive capacitance C) having one and other sides thereof alternately or periodically connected to associated sides of the element and to ground for simulating a floating bilinear resistor having a resistance R=T/C across the terminals which satifies the bilinear transformation s=(2(z-1/T)z+1). This circuit is insensitive to both top and bottom plate parasitic capacitance effects assocated with the capacitance when one terminal is connected to a voltage source and the other to a virtual ground point on the input to an operational amplifier. In alternate embodiments, the circuit simulates a grounded bilinear resistor when only one of the terminals is connected to ground, and when one terminal and one side of the capacitor are grounded.