Abstract: A switching device comprising a spring pileup assembly including a plurality of pairs of cantilevered stationary and movable contact springs secured between a pair of support members. A follower card is slidably mounted on the top portions of the support member allowing the follower to move in a plane 90 degrees to the contact springs. The tips of the movable contact springs protrude through openings in the follower card. A cam card including cam portions is slidably mounted to one of the support members perpendicular to the follower. As the cam card is moved the cams engage an edge of the follower causing it to be displaced in its plane of motion sufficiently to open a selected number of contact springs while allowing another selected number of contact springs to close.

Abstract: A subscriber station telephone circuit having a multiwinding transformer connected in a bridge configuration to couple the transmitter to the line and the balancing impedance in opposite phase. The receiver is magnetically coupled by the transformer so as to receive practically no side-tone during transmission. A varistor is employed as a regulator to control receiver signals.

Abstract: A circuit arrangement for combining a measure of the single phase error for a received data signal in a PSK demodulator with a measure of the direction of rotation of the receive data signal phasor between adjacent sample times for producing a timing phase error signal for controlling the phase of a local clock timing signal in the demodulator. In a demodulator producing a digital word defining differences between the phases of decoded phasors at adjacent sample times, a binary bit D.sub.k of the digital word may define the direction of rotation of the received signal phasor between the adjacent sample times. Sample values of the signal phase error signal in the demodulator are quantized into single binary bits E.sub.k indicating the sense of the signal phase error at sample times. In one circuit arrangement, binary bits E.sub.k and D.sub.k are combined in an exclusive-OR gate for producing a binary timing phase error bit M.sub.k.

Abstract: An error detector provides an output pulse whenever an error is detected in the framing pattern of a digital transmission system. A sample timer provides a sample pulse at the beginning of each sample interval and a sample clock pulse during the sample pulse. The sample interval includes a plurality of frames and the sample pulse occurs intermediate of the framing pattern. A logic arrangement is responsive to the error output pulse, the sample clock pulse and the sample pulse for providing an alarm indication when the number of error pulses equals or exceeds a first predetermined number during a sample interval. Conversely, the logic arrangement eliminates the alarm indication if the number of errors in a subsequent sample interval is less than a second predetermined number.

Abstract: A line voltage sensor and dial pulse repeater circuit for use in conjunction with a digital PABX telephone system connecting a subscriber station to a switching center providing for detection of off-hook condition of the subscriber's set, detection of irregularly shaped dial pulse and correction of the irregularly shaped dial pulses to allow accurate reconstruction of the dial pulses originally transmitted via the subscriber's set.

Abstract: A programmable power supply system which supplies all of the power requirements of a telephone subscriber's loop circuit in a digital telephone switching system. An associated processing unit generates digital control signals to select a particular power supply which generates power, of a particular magnitude in response to the control signals and applies same to a telephone subscriber's loop circuit.

Abstract: A multilayered thin film structure comprising layers of resistive and conductive materials on a substrate, said layers including tantalum nitride, palladium and gold. A layer of titanium nitride, is used between the tantalum nitride and palladium layers to act as an adhesive layer, to prevent undercutting during etching, and to allow all metal depositing to be performed during one step.

Abstract: A magnetic latching reed relay including a single continuous control winding disposed about an encapsulated reed switch having a pair of reeds constructed of a remanent magnetic material. The reeds are normally biased in an open position. When a first pulse of current, of a certain amplitude, is applied to the control winding a magnetic flux field is generated which magnetically saturates the reed blades, producing magnetic poles of opposite polarity at the contacting ends of the reeds which overcomes the normal mechanical bias of the blades, closing the contacts. A second pulse of current of an opposite direction and of approximately half the amplitude of the first pulse is then applied to the control winding and a reverse magnetic flux field is generated which is insufficient to magnetically saturate the reed blades and the magnetic polarity established thereby being also insufficient to overcome the normal spring bias of the blades, thus allowing the blades to return to the normal or open position.

Abstract: A device for the remote turn on of a teletypewriter of a distant terminal, such as at a hotel or motel. The turn on circuit is connected to the communication line to operate a magnetically latching relay. The latching relay operates to turn on the alternating current motor. The relay remains in its operated position until turned off by the end of message detector.

Abstract: An arrangement and method for locking an insulated electrical conductor to a slot-type terminal wherein a locking device is molded as part of the terminal base. As an insulated electrical conductor to be terminated is pushed into the slot-type terminal with a die type tool cutting edges of the die engage portion of the locking device, cutting it and cold forming the material about the conductor, thereby locking the conductor to the terminal base.

Abstract: A self-checking pulse density analyzer includes substantially similar first and second threshold detection circuits, each of which have one input connected to receive incoming pulse information to be analyzed, and each of which provide the same binary signal state at a separate output terminal, when the pulse density reaches a predetermined level. Each output terminal is connected to a separate input terminal of a threshold equalizing circuit and to respective inputs of first and second gating circuits. The threshold equalizing circuit is activated by the binary signal from the faster acting threshold detection circuit to speed up the operation of the slower threshold detection circuit and, thus, minimize the difference in operating time betwee the two circuits. These two nearly simultaneous binary indications cause the first gating circuit to operate and, thus, provide a particular binary output signal indicative thereof.

Abstract: The first monostable multivibrator of a series connected pair of monostable multivibrators is responsive to each break interval of input dial pulses for establishing a fixed time delay after which the second multivibrator initiates a corrected break interval and starts a first timing capacitor thereof charging at a rate set by a fixed time constant. Each input break interval also causes a capacitor of a second timing circuit to start discharging at a rate set by another fixed time constant, the time that the second capacitor starts discharging being a function of the pulse repetition frequency of input dial pulses. When the charge voltages on the two capacitors are the same values, the output of a comparator resets the second multivibrator to terminate an output break interval so as to cause corrected dial pulses in the output thereof to have a constant percent break.

Abstract: A regulating amplifier circuit with each transistor of a differentially connected pair thereof having a base electrode connected through an associated varistor to a first control transistor, the series combination of each varistor and the control transistor being driven by a variable DC bias voltage. The first control transistor is responsive to a gain control voltage for varying its conduction rate through the varistors and thus the gain of the circuit. A first resistor, the primary conduction path of a second control transistor, and a second resistor are electrically connected in series between a fixed DC supply voltage and a ground reference potential, with the second transistors collector voltage being coupled through an emitter follower as the bias voltage.

Abstract: In a thick film screen printer having a chute that is alternately in a horizontal position for receiving a screened substrate at one location on it and inclined downward to slide the screened substrate onto a conveyor belt, a pair of elongated openings extend through the chute at the one location. The broad side edges of the openings are generally parallel to each other and the direction that substrates slide off the chute. These broad edges are also inclined with respect to the top surface of this chute so the openings generally face toward each other. A stream of air is passed through one and then the other of these openings to alternately move substrates over them toward opposite sides of the chute so that they slide onto different transverse locations on the belt.

Abstract: An improved circuit for interfacing between a test desk, a subscriber line and an electronic switching center is disclosed herein. The disclosed improvements allow the relay circuit to operate in response to a predetermined threshold current value while requiring only a minimal current flow and thereby providing the capability to use components lower rated in terms of power consumption.

Abstract: A frame search control circuit for a digital transmission system includes an eight bit preview store and a four stage counter. At the beginning of each frame a timing device causes the eight stored bits to be sequentially read out into a comparator for a comparison with bits from the incoming bit stream. The incoming bits are stored in the preview store simultaneously with the read out to the comparator. For an in-frame condition only the first comparison is important and the remaining comparisons are ignored. Further, a count of eight is loaded into the four stage counter which limits the count to eight allowing only eight bits from the incoming bit stream to be read into the preview store, the framing bit being read in first so as to be available for comparison at the next framing interval. For an out-of-frame condition, the timing device initiates the sequential comparison beginning with the framing interval and in this case, each comparison is important.

Abstract: A private automatic branch exchange employing time division switching of digital signals, with provision for interfacing a fixed format data channel source to the randomly assigned channel allocation of the exchange. This is accomplished via channel buffering and channel address conversion under control of the branch exchange clock system.

Abstract: Groups of analog trunks are shown connected to analog to digital converters. The converters are each assigned a time during which their associated trunks may access a common data bus to the pulse code time division switching system. Provision is made for the use of T1 carrier channels to utilize the times normally assigned for the analog trunks by the provision of a circuit that one excludes the other from accessing the bus.