Patents Assigned to GTRAN, Inc.
  • Patent number: 8310310
    Abstract: An integrator circuit cancels a DC offset component related to an average DC value of a burst mode input signal from the output of an amplifier. The integrator circuit outputs an average DC value of the input signal in a response time that is shorter than the preamble of a burst mode signal. The integrator output signal remains stable within selected amplitude limits for a length of time corresponding to the data portion of a burst mode signal. A transimpedance amplifier embodiment of the invention comprises a TIA gain stage, an integrator, and a voltage-controlled current course. Other embodiments comprise an amplifier for converting single-ended input signals to differential output signals, an amplifier for differential output offset cancellation, a monolithic semiconductor integrated circuit die, and a packaged semiconductor integrated circuit device.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: November 13, 2012
    Assignee: Gtran Inc.
    Inventors: Zhihao Lao, Hehong Zou
  • Patent number: 6645819
    Abstract: One embodiment of the present invention provides a method of fabricating a semiconductor device including the steps of forming a first semiconductor layer; forming a second semiconductor layer over the first semiconductor layer; forming a mask over a first portion the second semiconductor layer; removing a second portion of the second semiconductor layer not covered by the mask; forming a first electrical connector on the first semiconductor layer; and forming a second electrical connector on the first portion of the second semiconductor layer.
    Type: Grant
    Filed: October 19, 2001
    Date of Patent: November 11, 2003
    Assignee: GTRAN, Inc.
    Inventor: Rajashekhar Pullela
  • Patent number: 6623180
    Abstract: One embodiment of the present invention provides a module including a primary substrate defining a base of the module, wherein the primary substrate is provided with a plurality of vias for electrical connection to a photodetector located within an interior portion of the module; a side wall member joined to the primary substrate to form side walls of the module and to define the interior portion of the module; a secondary substrate positioned within the interior portion of the module, the photodetector being mounted on the secondary substrate; an optical fiber guide extending into the interior portion of the module from outside the module, the optical fiber being arranged to receive an optical fiber and to position the optical fiber so that light emerging from the optical fiber impinges upon the photodetector; and a lid joined to the side wall member to enclose the interior portion of the module.
    Type: Grant
    Filed: October 19, 2001
    Date of Patent: September 23, 2003
    Assignee: GTRAN, Inc.
    Inventors: Ram Panicker, Ivair Gontijo, Yet-Zen Liu, Kirit Dharia, Robert Franks, Gary Lee Gutierrez