Abstract: In an integrated circuit device, a continuous-output, zero-standby-current non-volatile storage cell is formed by P-MOS and N-MOS transistor elements coupled in series between first and second power supply nodes (e.g., VDD and ground) and having a shared floating gate. When a positive charge is stored on the shared floating gate, the N-MOS transistor is switched to a conducting state, coupling the common-drain output of the transistor elements to the more negative power supply node to output a first logic value, and when a negative charge is stored on the shared floating gate, the P-MOS transistor element is switched to a conducting state, coupling the common-drain output to the more positive power supply node to output a second logic value.