Abstract: The invention relates to the technical field of microprocessors, in particular to a renaming method and system of fixed constant related instructions. The invention classifies the instructions in the decoder according to the characteristics of the instructions, and selects the instructions with fixed constants. In the renaming stage, the invention maps the source register and the destination register of such instructions to different fixed constant physical registers according to different fixed constants, updates the register renaming mapping tables SPEC_MAP and ARCH_MAP, and releases the physical registers corresponding to the fixed constant when the instruction is submitted, thereby realizing the function of the instruction. The invention classifies the instruction, and the fixed constant instruction does not need to enter the execution unit, but realizes the execution of the instruction through the renaming method, and the instruction execution efficiency is high.

Abstract: The invention relates to the technical field of a microprocessor, in particular to a method and a system for realizing the residual instruction of the RISC-V instruction set. The invention executes the CPU out of order, and the instruction enters the instruction decoding unit from the fetch unit to carry out instruction decoding; the instruction after decoding is renamed in the renaming unit, and the remainder instruction is optimized at the same time. If the remainder instruction does not meet the optimization condition, the renamed instruction enters the reservation station and then enters the execution unit for execution; the executed instruction is submitted through the reordering cache and the division instruction encoding cache resources allocated in the renaming phase are released. In the renaming stage, the invention realizes the function of the remainder instruction by adding the residue instruction acceleration unit.

Abstract: The invention relates to the technical field of a processor, in particular to a method for parallel extracting instructions and a readable storage medium. The method generates a valid vector of fetched instructions according to the end position vector s_mark_end of the instruction, and performs parallel decoding of instructions at each position, calculation of instruction address and branch instruction target address operation through logical “AND” and logical “OR” operations. Ultimately, multiple instructions are fetched in parallel. The present invention is a method for generating a valid vector of fetching instructions according to the end position vector s_mark_end of the instruction, and extracting multiple instructions in parallel through logical “AND” and logical “OR” operations. The invention can extract a plurality of instructions in parallel, there is no serial dependence relationship between each instruction, and the time sequence is easy to converge, so a higher main frequency can be obtained.

Abstract: The invention relates to the technical field of CPUs, in particular to a method and system for implementing a risc_v vector instruction set vsetvli instruction. it allocates vectag[n:0] information in the rename module when the CPU executes out of order, and determines whether the instruction is vsetvli. If the instruction is vsetvli, vectag+1 is added. If it is a non-vsetvli instruction, the vectag remains unchanged; it is sent to the execution unit, and the vsetvli instruction is distributed to the csr module; and the corresponding other vector instructions are distributed to the vpu module. The non-vsetvli{i} Vector instruction execution efficiency of the present invention is high. Data is selected by mask, which reduces power consumption, reduces execution cycle and latency, and has strong market application prospects.