Abstract: The display panel provided in the present application includes the substrate and the first conductive layer, the first insulating layer, the second conductive layer, the second insulating layer, the common electrode, and the connecting electrode disposed on the substrate in layers. The first insulating layer is provided with a first hole, the first hole exposes the first conductive layer, and the second conductive layer contacts the first conductive layer through the first hole. The second insulating layer is provided with a second hole, and the second hole exposes the second conductive layer. An orthographic projection of the second hole on the substrate overlaps with an orthographic projection of the first hole on the substrate.

Abstract: The present disclosure provides a method for manufacturing a thin film transistor array substrate and a display panel. The method includes: forming a plurality of dispersed metal oxide grains on a substrate; forming an amorphous metal oxide semiconductor layer in contact with the plurality of metal oxide grains, and at least one metal element in the metal oxide grain is same as metal elements in the metal oxide semiconductor layer; performing an annealing process on the amorphous metal oxide semiconductor layer, to obtain a crystallized metal oxide semiconductor layer.

Abstract: A display panel and a display device are disclosed. The display panel includes a first substrate, a second substrate, and a liquid crystal layer. The first substrate includes a first base, a thin film transistor layer, and a plurality of pixel electrodes. The thin film transistor layer includes an insulating layer and a plurality of data lines. The data lines are divided into a plurality of first subsections corresponding to the pixel electrodes. A sum of thicknesses of the insulating layer and the first base corresponding to positions of the first subsections is less than a sum of thicknesses of the insulating layer and the first base corresponding to positions of the pixel electrodes.

Abstract: An array substrate, a manufacturing method thereof, and a display panel thereof are disclosed. The array substrate includes: an underlay; a first insulation layer; a first active layer; a protective layer; a first gate electrode disposed on the first active layer at an interval from the protective layer; a second insulation layer; and a first source electrode and a first drain electrode, wherein the first source electrode and the first drain electrode are connected to the protective layer through first via holes in the second insulation layer; wherein a material of the protective layer includes indium tin oxide or indium gallium zinc oxide.

Abstract: The present application provides a display panel and a display device. The display panel includes a substrate, a gate electrode, an insulating barrier layer, and an active layer. The active layer is disposed on a side of the gate electrode away from or close to the substrate, and the insulating barrier layer is disposed between the gate electrode and the active layer; wherein band gap widths of materials of the insulating barrier layer are greater than a work function of a material of the gate electrode.

Abstract: A light-emitting module and a display device are provided. Reflective units are disposed, which include a main body disposed on a backplate and a reflective part disposed on the main body. The main body is provided with a retaining wall structure on one side away from the backplate, and an orthographic projection of the reflective part on the backplate covers an orthographic projection of the main body on the backplate, thereby effectively blocking a flow of a material of the reflective part, thereby controlling a height of the reflective part.

Abstract: A display panel and a display device are disclosed in the present application. The display panel includes a plurality of data lines, a Demux circuit, a plurality of signal lines, and at least one signal adjusting trace. Wherein the signal adjusting trace and corresponding signal lines are disposed in different layers and intersect with each other, along a second direction, the signal adjusting trace is configured to output a voltage adjusting signal at least before a next controlling signal is output by controlling traces, to adjust a voltage value of a next data voltage output by the signal line within an output period of the voltage adjusting signal.

Abstract: The present application discloses a display panel. The display panel includes a light-emitting layer and an adjustment layer. The light-emitting layer includes multiple light-emitting unit groups arranged along a first direction. Each light-emitting unit group includes at least one light-emitting unit. The multiple light-emitting unit groups includes one visual center unit group. Multiple adjustment unit groups have multiple thicknesses, and heights of the light-emitting unit groups located on the two sides of the visual center unit group are smaller than a height of the visual center unit group.

Abstract: A drive backplane and a method for preparing same, a light-emitting substrate and a method for preparing same. The drive backplane includes a driving substrate, a reflective layer, and a number of barriers, wherein the driving substrate includes a base substrate and connecting components disposed on the base substrate, and the connecting components are used to connect to light-emitting devices. The drive backplane can avoid a phenomenon that the reflective layer covers the connecting components, and the reflective layer covers a larger area on the drive backplane and reflectivity is relatively high.

Abstract: The present invention provides an array substrate, a method for manufacturing the array substrate, and a display panel. The array substrate includes a driving transistor, and the driving transistor includes: a gate electrode; an active layer arranged opposite to a position of the gate electrode, the active layer includes a first semiconductor and second semiconductors, the second semiconductors are in contact with the first semiconductor to form a first PN junction and a second PN junction respectively, and the first PN junction corresponds to the source electrode; and a source drain layer, including a source electrode and a drain electrode. The second semiconductors are electrically connected with the source electrode and drain electrode, respectively.

Abstract: A display substrate, a method for fabricating the same, and a vapor deposition apparatus are provided. The display substrate comprises two first overlapping areas, and further comprises a light-emitting functional layer and an electrode layer. The light-emitting functional layer comprises two second portions respectively located in the two first overlapping areas and each comprising a plurality of first blocks. The electrode layer comprises two fourth portions respectively located in the two first overlapping areas and each comprising a plurality of second blocks. In one same first overlapping area, each of the first blocks does not overlap at least partially with one of the second blocks.

Abstract: The present application provides a pixel driving circuit and a display panel. The pixel driving circuit includes a light emitting device, a voltage conversion module electrically connected to the light emitting device via a first node, a driving module electrically connected to the light emitting device via a second node, a data writing module electrically connected to the driving module via a fourth node, a first potential coupling module electrically connected to the second node and the third node, a second potential coupling module, and a first voltage terminal. Before the driving module controls a moment when the light emitting device starts to emit light, the voltage conversion module controls the potential of the first node to change from a first voltage to a second voltage, first potential coupling module couples potential of the third node, and second potential coupling module couples potential of the fourth node.

Abstract: An array substrate, a manufacturing method of the array substrate, and a display panel are provided. The array substrate includes a metal light-shielding layer, a buffer layer an active layer, an interlayer insulating layer, and a source-drain electrode layer, a plurality of first via holes are disposed in the interlayer insulating layer, the active layer includes a metal oxide body layer and an etching barrier layer disposed on a surface of the metal oxide body layer, the etching barrier layer includes a plurality of first etching barrier sections corresponding to the first via holes, and the source-drain electrode layer is electrically connected to the metal oxide body layer through the first etching barrier sections.

Abstract: A display panel and a display device are provided. The display panel includes a first substrate, a second substrate, and a sealant layer. The first substrate includes a ground electrode positioned in a frame region. The second substrate includes a black matrix layer and a protective layer. The protective layer is positioned on a side surface of the black matrix layer close to the first substrate. In the present application, at least one opening is arranged on the protective layer positioned in the frame region, so that the black matrix layer is exposed. By arranging the conductive adhesive in the sealant layer or forming the sealant layer with the conductive adhesive, the black matrix layer can be electrically connected to the ground electrode of the first substrate through the conductive adhesive.

Abstract: A display panel includes a gate electrode, a source electrode, a drain electrode, and a metal oxide layer disposed corresponding to the gate electrode. The metal oxide layer includes a lower metal oxide layer and an upper metal oxide layer stacked on the lower metal oxide layer. The lower metal oxide layer includes an indium oxide and a lanthanoid oxide. The upper metal oxide layer is located on a surface of the lower metal oxide layer adjacent to the source electrode and the drain electrode. The source electrode and the drain electrode are connected to the upper metal oxide layer. The upper metal oxide layer includes an indium oxide and a lanthanoid oxide, and the upper metal oxide layer includes polycrystalline phase.

Abstract: Provided is a array substrate, a manufacturing method thereof, and a display panel. The array substrate comprises a laminated substrate, a first insulating layer, a second insulating layer, and a third insulating layer, wherein a horizontal etching rate of the second insulating layer is less than that of the first insulating layer and the third insulating layer. The array substrate comprises a first region provided with a first type of via holes and a second region provided with a second type of via holes, the first type of via holes penetrates through the first, second and third insulating layers, and the second type of via holes penetrates through the third insulating layer. In the present disclosure, undercut structures formed in the first type of via holes can be eliminated through two etching processes, thus avoiding over-etching of the second type of via holes.

Abstract: An array substrate includes a first electrode, scanning lines extending along a first direction, data lines, and common signal lines. The data lines and the common signal lines extend along a second direction. The first electrode includes a first and a second sub-electrode. Each data line is disposed between two common signal lines. Two scanning lines, two common signal lines, and a data line define a first and a second sub-pixel area. The first and the second sub-electrode are disposed within the first and the second sub-pixel area respectively. The first sub-electrode includes a first main portion disposed close to a common signal line and first branch portions spaced along the second direction. A first space is defined between two adjacent first branch portions. Ends of the first branch portions are connected to the first main portion. Another ends of the first branch portions are spaced with a first space.

Abstract: A display panel and a method for fabricating the same are provided. The display panel includes a transistor layer. The transistor layer includes an oxide active layer and a first photocatalytic layer that are stacked. The first photocatalytic layer is made of a first material and a second material. A conduction band energy level of the first material is staggered from a conduction band energy level of the second material, or a valence band energy level of the first material is staggered from a valence band energy level of the second material. At least one of the conduction band energy level of the first material and the conduction band energy level of the second material is less than 0 eV.

Abstract: An array substrate and a display panel are disclosed. The array substrate includes a substrate, a first metal layer, a gate insulating layer, a semiconductor layer, and a second metal layer. The second metal layer includes a first block layer, a conductive layer, and a second block layer. By setting a redox potential of the first block layer to be less than a redox potential of the conductive layer, the first block layer is easier to be etched during galvanic corrosion compared with the conductive layer. Therefore, a taper angle of the second metal layer is reduced, and a tip is eliminated.

Abstract: An array substrate and a display panel are disclosed. The display panel includes the array substrate. An ion injection stopper layer and an active layer of the array substrate correspond to at least part of the channel part. The ion injection stopper layer blocks ions from being injected into the channel part. Therefore, an effective channel length of oxide TFTs is reduced. A width of a channel of the oxide TFTs can be reduced without changing a width-length ratio of the oxide TFTs. As such, a size of the oxide TFTs can be reduced, and an aperture ratio of the display panel is increased.