Abstract: The present subject matter is directed to a high-speed high resolution and accuracy time interpolator circuit. The interpolator uses basic dual ramp time-to-digital converter architecture, but provides circuits and methodologies to improve the accuracy, reduce the effective intrinsic jitter, and reduce the measurement time. Improved aspects of the present subject matter correspond to the introduction of a current mirror for improved settling time, a high frequency clock for improved resolution and ADC sample processing to improve resolution and accuracy.

Abstract: The present subject matter is directed to a high-speed high resolution and accuracy time interpolator circuit. The interpolator uses basic dual ramp time-to-digital converter architecture, but provides circuits and methodologies to improve the accuracy, reduce the effective intrinsic jitter, and reduce the measurement time. Improved aspects of the present subject matter correspond to the introduction of a current mirror for improved settling time, a high frequency clock for improved resolution and ADC sample processing to improve resolution and accuracy.

Abstract: The present subject matter is directed to methodologies for measuring jitter spectral content in a sampled signal using continuous time interval analyzers (CTIA) for characterization and test of clock signals and high-speed digital interfaces. The methodology takes advantage of anti-aliasing aspects of random sampling (RS) in a time interval error (TIE) based analysis methodology by randomizing timing of samples relative to signal edges and/or intervals between signal edges.

Abstract: Methodologies are disclosed for analyzing periodic jitter is a signal pattern using a continuous time interval analyzer. Sampled signal patterns may be correlated using time interval error calculations to determine start and stop sequences within sampled blocks of signal data while sampling synchronization may be achieved based on time interval calculations or pattern interval error calculations.

Abstract: The present subject matter is directed to a high-speed high resolution and accuracy time interpolator circuit. The interpolator uses basic dual ramp time-to-digital converter architecture, but provides circuits and methodologies to improve the accuracy, reduce the effective intrinsic jitter, and reduce the measurement time. Improved aspects of the present subject matter correspond to the introduction of a current mirror for improved settling time, a high frequency clock for improved resolution and ADC sample processing to improve resolution and accuracy.

Abstract: Methodologies are disclosed for analyzing periodic jitter is a signal pattern using a continuous time interval analyzer. Sampled signal patterns may be correlated using time interval error calculations to determine start and stop sequences within sampled blocks of signal data while sampling synchronization may be achieved based on time interval calculations or pattern interval error calculations.

Abstract: A system and method of estimating random and periodic phase noise components based on measurement of phase jitter in a given signal uses a difference filter to attenuate low frequency random noise components and a process of obtaining timing measurements at a plurality of sampling frequencies in order to de-alias identified noise spurs. Such technology is especially well-suited for devices capable of undersampling a jitter signal, such as continuous time interval analyzers (CTIAs).

Abstract: A system and related method for generating a test signal with controllable amounts of signal jitter includes a pattern generator, a programmable arbitrary waveform generator (AWG) and a phase modulator. The pattern generator is configured to generate a data signal characterized by a given data pattern, bit rate and pattern length. A trigger signal representative of initial timing information associated with the data signal is provided to the AWG which subsequently generates a modulation signal with a frequency equal to the bit rate divided by the pattern length of the data signal. This modulation signal is provided to the phase modulator, along with a reference clock signal, and the phase modulator generates a modulated clock signal controlled by a phase modulation means (e.g., a controllable delay line) fed by the modulation signal.

Abstract: Methods for estimating data-dependent jitter (DDJ) from measured samples of a transmitted data signal include a first exemplary step of obtaining a plurality of measurements (e.g., time tags and event counts for selected pulse widths in the data signal). Such measurements may be obtained at predetermined intervals within a transmitted signal or may be obtained at randomly selected intervals, and should yield measurements for each data pulse in a repeating data pattern. An average unit interval value representative of the average bit time of the transmitted signal is determined. Time interval error estimates representative of the timing deviation from each signal edge's measured value relative to its ideal value (determined in part from the calculated average unit interval value) are also determined, as well as a classification for each measured signal edge relative to a corresponding data pulse in the repeating data pattern.

Abstract: The present subject matter relates to methodologies for providing error correction compensation to measurement systems. Data-dependant jitter may be compensated by examining both short-term and long-term bit histories after applying a predetermined synthesized calibration pattern having selected characteristics to the measurement system. Neural networks may be provided to produce error correction signals that may be applied to measured data on a bit-by-bit basis to correct jitter. The synthesized calibration sequence may correspond to a base pattern having two segments; a first segment may correspond to a copy of the base pattern while the second segment may be a copy of the base pattern with some sections inverted.

Abstract: The present technology involves an apparatus and method for calibrating a plurality of distinct signal paths connecting a device under test (DUT) to a time measurement device. The disclosed calibration circuit, which may be connected to the test setup throughout the testing process, measures the signal skew associated with each distinct signal path connecting a DUT, such as an integrated circuit, to a time measurement device, such as a time interval analyzer. The measured skew values, which may be collected throughout the testing process, are stored in memory. Such memory may be within the time measure device, an external storage device or a computing device that may be in communication with the time measurement device. The time measurement device uses the stored skew values to adjust the test signals to compensate for signal path related signal skew. In addition, the stored skew values are used to perform signal path diagnostics.

Abstract: A system and corresponding method for measuring relative timing of signal events in at least one measurement signal includes input circuitry for receiving such a measurement signal. The input circuitry may include a comparator configured to convert the measurement input signal into a binary timing signal that is indicative of selected transitions, or signal events, in the measurement signal. The original measurement signal, or subsequently generated timing signal, is then provided to signal splitting circuitry that is configured to split such signal a predetermined number of times and to generate a plurality of data streams whose frequency level is lower than the frequency level of the original measurement signal.

Abstract: A system for calibrating cables attached to a time measurement device is disclosed. The system includes a calibration device that generates a plurality of synchronized measurement signals that are communicated to a time measurement device by a set of cables. The calibration device can also generate at least one arming signal that is also communicated to the time measurement device. By determining the relative arrival time of a common reference event of each of the measurement signals, the time measurement device can determine any skew that exists between each of the cables that input the measurement signals. The skew can then be used to compensate for varying cable skew in future time measurements. In one embodiment, the system of the present invention can also be used to determine the arming latency of the time measurement device by delaying the measurement signals in relation to the arming signals and observing the delay time which causes complete synchronization of the measurement signals.

Abstract: A method for calibrating cables attached to a time measurement device is disclosed. Such a method may utilize a system including a calibration device that generates a plurality of synchronized measurement signals that are communicated to a time measurement device by a set of cables. By determining the relative arrival time of a common reference event of each of the measurement signals, the time measurement device can determine any skew that exists between each of the cables that input the measurement signals. The skew can then be used to compensate for varying cable skew in future time measurements. In one embodiment, the method can also be used to determine the arming latency of the time measurement device and by delaying the measurement signals in relation to the arming signals and observing the delay which causes complete synchronization of the measurement signals.

Abstract: A system for calibrating cables attached to a time measurement device is disclosed. The system includes a calibration device that generates a plurality of synchronized measurement signals that are communicated to a time measurement device by a set of cables. The calibration device can also generate at least one arming signal that is also communicated to the time measurement device. By determining the relative arrival time of a common reference event of each of the measurement signals, the time measurement device can determine any skew that exists between each of the cables that input the measurement signals. The skew can then be used to compensate for varying cable skew in future time measurements. In one embodiment, the system of the present invention can also be used to determine the arming latency of the time measurement device by delaying the measurement signals in relation to the arming signals and observing the delay time which causes complete synchronization of the measurement signals.

Abstract: A method for calibrating cables attached to a time measurement device is disclosed. Such a method may utilize a system including a calibration device that generates a plurality of synchronized measurement signals that are communicated to a time measurement device by a set of cables. By determining the relative arrival time of a common reference event of each of the measurement signals, the time measurement device can determine any skew that exists between each of the cables that input the measurement signals. The skew can then be used to compensate for varying cable skew in future time measurements. In one embodiment, the method can also be used to determine the arming latency of the time measurement device and by delaying the measurement signals in relation to the arming signals and observing the delay which causes complete synchronization of the measurement signals.

Abstract: A time interval analyzer for measuring time intervals between events in an input signal includes a trigger circuit that receives the input signal and that outputs a time trigger signal at a first triggering level upon occurrence of a first input signal event. A time counter receives a time base signal and increments a time count at each period of the time base signal. The time count is calibrated to a predetermined reference time. A processor circuit is in communication with the trigger circuit and the time counter so;that the processor circuit receives the time trigger signal and reads the time count from the time counter. The processor circuit is configured to read the time count upon receiving the time trigger signal at the first triggering level so that the time count read by the processor circuit indicates the time at which the first input signal event occurred with respect to the predetermined reference time.

Abstract: A time interval analyzer includes a trigger circuit that receives an input signal and that outputs a trigger signal at a triggering level upon occurrence of a first event. A first counter receives the input signal and, when it is activated, increments a count at each occurrence of an event. A second counter receives the input signal and, when it is activated, increments a count at each occurrence of an event. A control circuit receives the trigger signal from the trigger circuit and outputs a control signal to each of the first counter and the second counter that controls activation of the first counter and the second counter so that only one of the first counter and the second counter is activated at a time.

Abstract: A time interval analyzer includes a signal channel that receives an input signal. A plurality of measurement circuits are defined within the signal channel in parallel with each other. Each measurement circuit is configured to receive the input signal, measure an occurrence of a first event of the input signal with respect to a predetermined time reference and to output a time signal corresponding to the measurement of the occurrence. A processor circuit is in communication with the signal channel. It is configured to receive and compare time signals from the measurement circuits to each other to determine a time interval between the first event measured by a first measurement circuit and an event measured by a second measurement circuit.

Abstract: A time interval analyzer for measuring time intervals between events in an input signal includes a trigger circuit that receives an input signal and that outputs a trigger signal at a triggering level upon occurrence of a first event and at a non-triggering level upon occurrence of a reference event that follows the first event. A first current circuit has a current source or a current sink. A second current circuit has a current sink or a current source. A capacitor and a shunt are operatively disposed in parallel with respect to the first current circuit. The shunt is disposed between the first current circuit and the second current circuit. The shunt receives the trigger signal and is selectable between conducting and non-conducting states so that the shunt is driven to the conducting state upon receiving the trigger signal at the triggering level and is driven to the non-conducting state upon receiving the trigger signal at a non-triggering level.