Patents Assigned to H. Terada
  • Patent number: 5410362
    Abstract: A signal input in a raster scan format is entered into one-dimensional digital filters. An output of the one-dimensional digital filter is multiplied in a multiplier. Outputs of one-dimensional digital filters are provided to delay circuits to generate a time delay in a direction perpendicular to the raster scan direction. The output of the multiplier and the outputs of the delay circuits are added by adders. A one-dimensional digital filter of the vertical direction is decomposed in a manner more simple than in the horizontal direction to reduce delay time between input and output.
    Type: Grant
    Filed: September 3, 1993
    Date of Patent: April 25, 1995
    Assignees: H. Terada, Mitsubishi Denki Kabushiki Kaisha, Sharp Kabushiki Kaisha
    Inventors: Hiroaki Terada, Makoto Iwata, Masayuki Mizuno