Abstract: An apparatus supports single root input/output virtualization (SR-IOV) capable devices. The apparatus includes input/output ports, and SR-IOV capable PCIe devices. Each SR-IOV capable PCIe device has one or more namespaces or controller memory buffers. The SR-IOV capable PCIe device provides one or more physical functions and virtual functions that can access the one or more namespaces or controller memory buffers. A PCIe switch controller communicates with host servers coupled to the input/output ports, and assigns one or more virtual functions to each host device, and enables the host devices to access one or more namespaces or controller memory buffers through the assigned virtual functions.

Abstract: An apparatus supports single root input/output virtualization (SR-IOV) capable devices. The apparatus includes input/output ports, and SR-IOV capable PCIe devices. Each SR-IOV capable PCIe device has one or more namespaces or controller memory buffers. The SR-IOV capable PCIe device provides one or more physical functions and virtual functions that can access the one or more namespaces or controller memory buffers. A PCIe switch controller communicates with host servers coupled to the input/output ports, and assigns one or more virtual functions to each host device, and enables the host devices to access one or more namespaces or controller memory buffers through the assigned virtual functions.

Abstract: An apparatus supports single root input/output virtualization (SR-IOV) capable devices. The apparatus includes input/output ports, and SR-IOV capable PCIe devices. Each SR-IOV capable PCIe device has one or more namespaces or controller memory buffers. The SR-IOV capable PCIe device provides one or more physical functions and virtual functions that can access the one or more namespaces or controller memory buffers. A PCIe switch controller communicates with host servers coupled to the input/output ports, and assigns one or more virtual functions to each host device, and enables the host devices to access one or more namespaces or controller memory buffers through the assigned virtual functions.

Abstract: A system for managing software-defined persistent memory includes a CPU, a PCIe switch, one or more random access memory modules, and one or more NVMe SSDs. The PCIe switch is configured to communicate with one or more host devices. The CPU and the PCIe switch are configured to generate, for each host device, a persistent memory controller data structure that has configuration data to enable the CPU and the PCIe switch to emulate a persistent memory controller when interacting with the host device. The CPU and the PCIe switch are configured to receive instructions from the one or more host devices and persistently store write data in one or more NVMe SSDs or retrieve read data from the one or more NVMe SSDs based on the instructions from the one or more host devices, and use at least a portion of the RAM as cache memory to temporarily store at least one of the read data from the one or more NVMe SSDs or the write data intended to be persistently stored in the one or more NVMe SSDs.

Abstract: Direct memory access (DMA) is provided in a computing system that includes a central processing unit (CPU), CPU memory associated with the CPU, a graphics processing unit (GPU), GPU memory associated with the GPU, a storage device capable of direct memory access, and a peer-to-peer host bus to which the other components are electrically coupled, directly or indirectly. For each page of the GPU physical memory, a data structure representing the page of GPU physical memory is generated, a GPU virtual memory space is allocated, the GPU virtual memory space is mapped to a GPU physical memory space. Based on the data structure representing the page of GPU physical memory, the GPU physical memory space is mapped to a CPU virtual address associated with a user-space process.

Abstract: An apparatus allocation controller includes a control circuit, a bus, and a read-only memory. The control circuit includes multiple switch chipsets. The switch chipsets are electrically connected to multiple servers through multiple connection ports. The bus is electrically connected to multiple peripheral apparatuses. The control circuit sets a unique identifier belonging to the apparatus allocation controller and writes the unique identifier to a read-only memory of each of the switch chipsets. The control circuit determines a resource allocation table according to the unique identifier of the apparatus allocation controller, a plurality of switch chipset serial numbers corresponding to the switch chipsets and a plurality of station numbers. The resource allocation table is configured to recognize resource usage statuses of the servers using the peripheral apparatuses through the apparatus allocation controller. In addition, a resource allocation system and an apparatus recognizing method are also provided.

Abstract: An apparatus assigning controller is provided. The apparatus assigning controller includes a plurality of peripheral apparatuses, a processor, and a communication interface. The peripheral apparatuses and the communication interface meet the peripheral component interconnect express. The processor is coupled to the peripheral apparatuses by a bus meeting the peripheral component interconnect express. The communication interface is coupled to the processor. A server is coupled to the apparatus assigning controller through the communication interface. When the server is started, the processor receives an apparatus scanning requirement of the server, and provides a predetermined apparatus information to the server, wherein the server reserves a corresponding hardware resource and a corresponding memory space according to the predetermined apparatus information.

Abstract: An apparatus allocating controller is provided in the invention. The apparatus allocating controller includes a bus, a communication interface, and a processor. The bus is coupled to a peripheral apparatus, and the peripheral apparatus meets the peripheral component interconnect express. The communication interface is coupled to a server. The apparatus allocating controller and the peripheral apparatus communicate with the server through the communication interface. The processor is coupled to the bus. The processor is configured to allocate the peripheral apparatus to the server, and monitors the connection status of the peripheral apparatus and the bus. When another peripheral apparatus hot plugs in the bus so that a hot-plug event occurs on the bus, the processor determines whether the another peripheral apparatus has a physical function or a virtual function, and the processor reallocates the peripheral apparatus to the server according to the hot-plug event.

Abstract: An apparatus assigning controller is provided. The apparatus assigning controller includes a communication interface and a routing apparatus. The communication interface is configured to respectively connect to a plurality of external servers. The routing apparatus is connected to the communication interface. The routing apparatus is configured to provide a data transfer path between the plurality of servers, so as to connect the routing apparatus to the plurality of servers through the communication interface. The plurality of servers share data with each other via the routing apparatus according to a peripheral component interconnect express (PCI Express) communication protocol. A data sharing method is also provided.