Abstract: A method of manufacturing a semiconductor integrated circuit device including a memory cell array in which non-volatile semiconductor memory devices are arranged in a matrix of a plurality of rows and columns.

Abstract: A method is provided for programming data for a memory element of a twin memory cell (i). The word line WL1 is set to a programming word line selection voltage, the control gate CG[i+1] is set to a programming control gate voltage, and the control gate CG[i] is set to an over-ride voltage. The bit line BL[i+1] is set to a programming bit line voltage, and the bit line BL[i+2] is set to Vdd, but not to 0 V.

Abstract: A method is provided for programming data for a memory element of a twin memory cell (i). The word line WL1 is set to a programming word line selection voltage, the control gate CG[i+1] is set to a programming control gate voltage, the control gate CG[i] is set to an over-ride voltage, the bit line BL[i+1] is set to a programming bit line voltage, and the bit line BL[i] is connected to the constant current source.

Abstract: A method of fabricating a semiconductor device including the following steps of: forming a first insulating layer, a first conductive layer and a stopper layer over a semiconductor layer; forming a mask insulating layer on the first conductive layer in a logic circuit region; forming a conductive layer in a formation region of word gate layers and common contact sections and forming gate electrodes; anisotropically etching the second conductive layer to form control gates in the shape of sidewalls and a conductive layer of the common contact sections, in a memory region; and patterning the third conductive layer and the first conductive layer to form word gates and word lines.

Abstract: In the prior arts a twin MONOS memory erase is achieved by applying a positive bias to the bit diffusion and a negative bias to the control gate. The other word gate and substrate terminals are grounded. But the voltage of word gate channel adjacent to the control gate can dramatically influence erase characteristics and speed, due to the short control gate channel length, which is a few times of the carrier escape length. A negative voltage application onto the word gate enhances erase speed, whereas a positive channel potential under the word gate reduces erase speed. By effective biasing of the memory array, word line or even single memory cell level erase is possible without area penalty, as compared to erase blocking by triple well or physical block separations of prior art. Near F-N channel erase without substrate bias application and program disturb protection by word line voltage are also included.

Abstract: In the present invention a nonvolatile memory array architecture can be realized by a fabrication process more compatible to an MOS logic fabrication process as compared with previous nonvolatile memory array architectures. Higher write and/or read speed is possible because of a lower bit line resistance. A high hard bit density near 4F2 is possible when a self-align contact technology and a border less contact technology are used. Connection regions are formed throughout the memory array comprising four cells that are connected to one bit line. The connection regions can be formed in the same processing step with opposite conductivity regions for economy of processing. A plurality of memory cells are two dimensionally disposed in two different directions with connection regions, conductive bit lines extending in the first direction, conductive word lines extending in the second direction, and conductive control lines.

Abstract: A fabrication method of the present invention includes the following steps: A step of forming gate electrodes in a logic circuit region; a step of forming first and second protective insulating layers in the logic circuit region; a step of forming a first gate insulating layer and a word gate layer in a memory region; a step of forming a second gate insulating layer on a semiconductor substrate and forming side insulating layers on both sides of the word gate layer in the memory region; a step of anisotropically etching the second conductive layer, thereby forming control gates in the shape of sidewalls and a conductive layer continuous with the control gates in regions in which common contact sections are formed; a step of removing the first and second protective insulating layers; and a step of forming impurity layers which form either a source or drain.

Abstract: The present invention relates to a nonvolatile memory cell and/or array and a method of operating the same high integrated density nonvolatile memory cell enabling high integration density, low voltage programming and/or high speed programming, a method of programming same and a nonvolatile memory array. A p-well 101 is formed in a surface of a substrate 10 and a channel forming semiconductor region 110 is defined in a surface of the p-well 101 and separated by a first n+ region 121 and a second n+ region 122. A carrier-supplying portion (CS: carrier supply) 111 is formed coming into contact with the first n+ region 121 and a carrier-acceleration-injection portion 112 (AI: acceleration and injection) is in contact with the second n+ region 122 in the channel forming semiconductor region 110 wherein the carrier-supplying portion 111 and carrier-acceleration-injection portion 112 are in contact with each other.

Abstract: A fast low voltage ballistic program, ultra-short channel, ultra-high density, dual-bit multi-level flash memory is described with a two or three polysilicon split gate side wall process. The structure and operation of this invention is enabled by a twin MONOS cell structure having an ultra-short control gate channel of less than 40nm, with ballistic injection which provides high electron injection efficiency and very fast program at low program voltages of 3˜5V. The cell structure is realized by (i) placing side wall control gates over a composite of Oxide-Nitride-Oxide (ONO) on both sides of the word gate, and (ii) forming the control gates and bit diffusion by self-alignment and sharing the control gates and bit diffusions between memory cells for high density.

Abstract: An electrically programmable read only memory device which has efficiency of electron injection from channel to floating gate is provided. This memory cell includes a control gate and floating gate between source and drain regions. The region under the floating gate has extremely small enhanced mode channel and N region. Therefore, this channel is completely depleted by the program drain voltage. The enhanced mode channel region is precisely defined by the side wall spacer technique. Also, the N drain region is accurately defined by the difference of side wall polysilicon gate and the first spacer.

Abstract: A fabrication method for an electrically programmable read only memory device, which consists of a control/word gate and a MONOS control gate on the side wall of the control gate. The unique material selection and blocking mask sequences allow simple and safe fabrication within the delicate scaled CMOS process environment, of a sidewall MONOS control gate with an ultra short channel under the control gate, which involves double side wall spacer formation i.e., a disposable side wall spacer and the final polysilicon spacer gate.

Abstract: A new FET device configuration for electrically programmable memories (EPROM), flash/electrically erasable and programmable read-only memories (EEPROM), and non-volatile Random Access Memory (NVRAM) which adds vertical components to a previously planar floating gate cell structure; efficiency of electron injection from the channel to floating gate is enhanced by many orders of magnitude because electrons accelerated in the channel penetraite in the direction of movement, straight into the floating gate. The floating gate resides over a series of arbitrary horizontal and vertical channel region components, the key topological feature being that the vertical channel resides near the drain, allowing electrons to penetrate straight into the floating gate. In contrast, the prior art relies on the indirect process of electron scattering by phonon and the 90 degree upward redirection of motion to the floating gate used by conventional Channel Hot Electron EPROM and EEPROM cells.

Abstract: An fast program, ultra-high density, dual-bit, multi-level flash memory process, which can be applied to a ballistic step split gate side wall transistor, or to a ballistic planar split gate side wall transistor, which enables program operation by low voltage requirement on the floating gate during program is described. Two side wall floating gates are paired with a single word line select gate, and word lines are arranged to be perpendicular both the bit lines and control gate lines. Two adjacent memory cells on the same word line do not require an isolation region. Also, the isolation region between adjacent memory cells sharing the same bitline is defined by the minimum lithography feature, utilizing a self align fill technique. Adjacent memory cells on the same word line share bitline diffusion as well as a third poly control gate. Control gates allow program and read access to the individual floating gate.

Abstract: A fabrication method for an electrically programmable read only memory device, which consists of a control/word gate and a floating gate on the side wall of the control gate. The unique material selection and blocking mask sequences allow simple and safe fabrication within the delicate scaled CMOS process environment, of a side wall floating gate with an ultra short channel under the floating gate, which involves double side wall spacer formation i.e., a disposable side wall spacer and the final polysilicon spacer gate.

Abstract: In this invention a reference circuit is disclosed that produces a reference current to be used in determining the value of data in a flash memory cell. The memory cell current is compared to the reference current in a sense amplifier. A reference circuit that generates the reference current is connect to each bit line of the flash memory and uses bit lines that are not activated when a particular cell is being read to connect the reference current to the sense amplifiers. The use of a reference current allows multi-bit cells to be read by using a variation on the reference circuit that has a plurality of reference transistors creating a plurality of reference currents.. Verification of the programmed and erase states of a flash memory cell can be determined using different values of the reference current that are easily set in the reference circuit by changing a reference voltage.

Abstract: In this invention is described a circuit and method for auto programming of a flash memory cell of an EEPROM. A step split gate is used that has low voltage and low current program conditions. This allows a load device to be connected to each bit line, and sets up a voltage divider between the cell being programmed and the load device. The load device limits the programming current and provides programming data to the cell being programmed. The load device is shut off when the bit line voltage is reduced below a predetermined reference, ending programming of the flash memory cell. The source to drain voltage increases as the memory cell is programmed as a result of the voltage divider between the load device and the cell being programmed thus maintaining pinch off. This produces more energy to program the flash cell and with proper design allows the programming efficiency to be relatively constant over the time that elections are injected onto the floating gate of the flash memory cell.

Abstract: A method for fabricating an electrically programmable memory device which has efficiency of electron injection from the channel to floating gate is provided. A substrate is provided having source and drain region with a channel therebetween. A floating gate structure is formed over portions of the source and drain regions and the channel. The structure includes a dielectric layer and a conductor layer thereover. The channel under the floating gate has both horizontal and vertical components. After forming the vertical and horizontal components, an N- drain region is formed in self-alignment with the vertical channel step region's edge. The depth of the N- drain is greater than the source region.