Abstract: In the prior arts a twin MONOS memory erase is achieved by applying a positive bias to the bit diffusion and a negative bias to the control gate. The other word gate and substrate terminals are grounded. But the voltage of word gate channel adjacent to the control gate can dramatically influence erase characteristics and speed, due to the short control gate channel length, which is a few times of the carrier escape length. A negative voltage application onto the word gate enhances erase speed, whereas a positive channel potential under the word gate reduces erase speed. By effective biasing of the memory array, word line or even single memory cell level erase is possible without area penalty, as compared to erase blocking by triple well or physical block separations of prior art. Near F-N channel erase without substrate bias application and program disturb protection by word line voltage are also included.

Abstract: Provided in the present invention are a high speed and low program voltage nonvolatile memory cell, a programming method for same and a nonvolatile memory array. A nonvolatile memory cell comprises a first gate insulator formed on a surface of a first channel forming semiconductor region adjacent to a source region; a second gate insulator formed on a surface of a second channel forming semiconductor region adjacent to a drain region; a first gate electrode formed on said first gate insulator; and a second gate electrode formed on said second gate insulator wherein the second gate insulator includes a first layer forming a potential barrier at the interface with the second channel forming region; a third layer forming a potential barrier at the interface with the second gate electrode and the second layer between the first and third layers forming a carrier trapping level.

Abstract: An fast program, ultra-high density, dual-bit, multi-level flash memory process, which can be applied to a ballistic step split gate side wall transistor, or to a ballistic planar split gate side wall transistor, which enables program operation by low voltage requirement on the floating gate during program is described. Two side wall floating gates are paired with a single word line select gate, and word lines are arranged to be perpendicular both the bit lines and control gate lines. Two adjacent memory cells on the same word line do not require an isolation region. Also, the isolation region between adjacent memory cells sharing the same bitline is defined by the minimum lithography feature, utilizing a self align fill technique. Adjacent memory cells on the same word line share bitline diffusion as well as a third poly control gate. Control gates allow program and read access to the individual floating gate.

Abstract: An fast program, ultra-high density, dual-bit, multi-level flash memory process, which can be applied to a ballistic step split gate side wall transistor, or to a ballistic planar split gate side wall transistor, which enables program operation by low voltage requirement on the floating gate during program is described. Two side wall floating gates are paired with a single word line select gate, and word lines are arranged to be perpendicular both the bit lines and control gate lines. Two adjacent memory cells on the same word line do not require an isolation region. Also, the isolation region between adjacent memory cells sharing the same bitline is defined by the minimum lithography feature, utilizing a self align fill technique. Adjacent memory cells on the same word line share bitline diffusion as well as a third poly control gate. Control gates allow program and read access to the individual floating gate.

Abstract: In the present invention a nonvolatile memory array architecture can be realized by a fabrication process more compatible to an MOS logic fabrication process as compared with previous nonvolatile memory array architectures. Higher write and/or read speed is possible because of a lower bit line resistance. A high hard bit density near 4F2 is possible when a self-align contact technology and a border less contact technology are used. Connection regions are formed throughout the memory array comprising four cells that are connected to one bit line. The connection regions can be formed in the same processing step with opposite conductivity regions for economy of processing. A plurality of memory cells are two dimensionally disposed in two different directions with connection regions, conductive bit lines extending in the first direction, conductive word lines extending in the second direction, and conductive control lines.

Abstract: A wordline decoder for high density flash memory is described with negative voltage capability for memory operations such as erase. A main decoder is shared with a plurality of wordline driver circuits to reduce wiring congestion and overall layout size. In a second embodiment a wordline decoder for fast read access is provided in which a high speed positive voltage decoder is separate from the negative voltage decoder with the addition of a triple well NMOS transistor into the inverter driver circuits. The use of triple well NMOS transistors reduces circuit and layout complexity.