Patents Assigned to Halo LSI, Inc.
  • Patent number: 9153592
    Abstract: A charge trap type of memory having a memory channel with vertical and possibly horizontal components is described. The invention includes a new operation method of simultaneous hole and electron injection operation for high speed and high reliability non-volatile memories, as well as high-density non-volatile memories. Array implementations for high-density memory arrays and high-speed memory arrays and their fabrication methods are also described.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: October 6, 2015
    Assignee: Halo LSI, Inc.
    Inventors: Seiki Ogura, Tomoko Iwasaki, Nori Ogura
  • Patent number: 9123419
    Abstract: Methods of complementary pairing of memory cells are described. These methods include two physical memory cells in a complementary pair, a complementary pair of reference cells for each erase block, and a physical complementary pair storing multiple data bits.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: September 1, 2015
    Assignee: Halo LSI, Inc.
    Inventors: Nori Ogura, Tomoko Ogura, Seiki Ogura
  • Publication number: 20140219030
    Abstract: A charge trap type of memory having a memory channel with vertical and possibly horizontal components is described. The invention includes a new operation method of simultaneous hole and electron injection operation for high speed and high reliability non-volatile memories, as well as high-density non-volatile memories. Array implementations for high-density memory arrays and high-speed memory arrays and their fabrication methods are also described.
    Type: Application
    Filed: April 4, 2014
    Publication date: August 7, 2014
    Applicant: Halo LSI, Inc.
    Inventors: Seiki Ogura, Tomoko Iwasaki, Nori Ogura
  • Publication number: 20140133245
    Abstract: A stitch area configuration for word gates and control gates of a twin MONOS metal bit array comprises control gates on sidewalls of the word gates wherein the word gates and control gates run in parallel. Control gate poly contacts contact each of the control gates aligned in a row at the stitch area perpendicular to the control gates. Two word gate poly contacts at the stitch area contact alternating word gates. Also provided are bit lines, word line and control gate decoders and drivers, a bit line decoder, a bit line control circuit, and a chip controller to control the memory array. The invention also provides twin MONOS metal bit array operations comprising several control gates driven by one control gate driver circuit and one word gate driven by one word gate driver circuit, as well as erase inhibit and block erase.
    Type: Application
    Filed: January 20, 2014
    Publication date: May 15, 2014
    Applicant: Halo LSI, Inc.
    Inventors: Kimihiro Satoh, Tomoko Ogura, Ki-Tae Park, Nori Ogura, Yoshitaka Baba
  • Publication number: 20140133244
    Abstract: A stitch area configuration for word gates and control gates of a twin MONOS metal bit array comprises control gates on sidewalls of the word gates wherein the word gates and control gates run in parallel. Control gate poly contacts contact each of the control gates aligned in a row at the stitch area perpendicular to the control gates. Two word gate poly contacts at the stitch area contact alternating word gates. Also provided are bit lines, word line and control gate decoders and drivers, a bit line decoder, a bit line control circuit, and a chip controller to control the memory array. The invention also provides twin MONOS metal bit array operations comprising several control gates driven by one control gate driver circuit and one word gate driven by one word gate driver circuit, as well as erase inhibit and block erase.
    Type: Application
    Filed: January 20, 2014
    Publication date: May 15, 2014
    Applicant: Halo LSI, Inc.
    Inventors: Kimihiro Satoh, Tomoko Ogura, Ki-Tae Park, Nori Ogura, Yoshitaka Baba
  • Patent number: 8710576
    Abstract: A charge trap type of memory having a memory channel with vertical and possibly horizontal components is described. The invention includes a new operation method of simultaneous hole and electron injection operation for high speed and high reliability non-volatile memories, as well as high-density non-volatile memories. Array implementations for high-density memory arrays and high-speed memory arrays and their fabrication methods are also described.
    Type: Grant
    Filed: February 11, 2009
    Date of Patent: April 29, 2014
    Assignee: Halo LSI Inc.
    Inventors: Seiki Ogura, Tomoko Ogura Iwasaki, Nori Ogura
  • Patent number: 8633544
    Abstract: A stitch area configuration for word gates and control gates of a twin MONOS metal bit array comprises control gates on sidewalls of the word gates wherein the word gates and control gates run in parallel. Control gate poly contacts contact each of the control gates aligned in a row at the stitch area perpendicular to the control gates. Two word gate poly contacts at the stitch area contact alternating word gates. Also provided are bit lines, word line and control gate decoders and drivers, a bit line decoder, a bit line control circuit, and a chip controller to control the memory array. The invention also provides twin MONOS metal bit array operations comprising several control gates driven by one control gate driver circuit and one word gate driven by one word gate driver circuit, as well as erase inhibit and block erase.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: January 21, 2014
    Assignee: Halo LSI, Inc.
    Inventors: Kimihiro Satoh, Tomoko Ogura, Ki-Tae Park, Nori Ogura, Yoshitaka Baba
  • Publication number: 20130094299
    Abstract: Methods of complementary pairing of memory cells are described. These methods include two physical memory cells in a complementary pair, a complementary pair of reference cells for each erase block, and a physical complementary pair storing multiple data bits.
    Type: Application
    Filed: December 3, 2012
    Publication date: April 18, 2013
    Applicant: HALO LSI, INC.
    Inventors: Nori Ogura, Tomoko Ogura, Seiki Ogura
  • Publication number: 20130094303
    Abstract: Methods of complementary pairing of memory cells are described. These methods include two physical memory cells in a complementary pair, a complementary pair of reference cells for each erase block, and a physical complementary pair storing multiple data bits.
    Type: Application
    Filed: December 3, 2012
    Publication date: April 18, 2013
    Applicant: Halo LSI, Inc.
    Inventor: Halo LSI, Inc.
  • Patent number: 8325542
    Abstract: Methods of complementary pairing of memory cells are described. These methods include two physical memory cells in a complementary pair, a complementary pair of reference cells for each erase block, and a physical complementary pair storing multiple data bits.
    Type: Grant
    Filed: August 25, 2009
    Date of Patent: December 4, 2012
    Assignee: Halo LSI Inc.
    Inventors: Nori Ogura, Tomoko Ogura, Seiki Ogura
  • Patent number: 8174885
    Abstract: The present invention provides a novel read method of twin MONOS metal bit or diffusion bit structure for high-speed application. In a first embodiment of the present invention, the alternative control gates are set at the same voltage. In a second embodiment of the present invention, all the control gates are set at the operational voltage from the beginning. In both embodiments, the bit line and word gate are used to address the selected memory cell.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: May 8, 2012
    Assignee: Halo LSI Inc.
    Inventors: Tomoko Ogura, Nori Ogura, Seiki Ogura, Tomoya Saito, Yoshitaka Baba
  • Patent number: 8139410
    Abstract: A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.
    Type: Grant
    Filed: June 16, 2010
    Date of Patent: March 20, 2012
    Assignee: Halo LSI, Inc.
    Inventors: Tomoko Ogura, Seiki Ogura, Nori Ogura
  • Patent number: 8089809
    Abstract: A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.
    Type: Grant
    Filed: June 16, 2010
    Date of Patent: January 3, 2012
    Assignee: Halo LSI, Inc.
    Inventors: Tomoko Ogura, Seiki Ogura, Nori Ogura
  • Patent number: 8027198
    Abstract: A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.
    Type: Grant
    Filed: June 16, 2010
    Date of Patent: September 27, 2011
    Assignee: Halo LSI, Inc.
    Inventors: Tomoko Ogura, Seiki Ogura, Nori Ogura
  • Patent number: 8023326
    Abstract: A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.
    Type: Grant
    Filed: June 16, 2010
    Date of Patent: September 20, 2011
    Assignee: Halo LSI, Inc.
    Inventors: Tomoko Ogura, Seiki Ogura, Nori Ogura
  • Patent number: 7936604
    Abstract: The present invention provides a novel operational method of twin MONOS metal bit or diffusion bit structure for high-speed application. In a first embodiment of the present invention, the alternative control gates are set at the same voltage. In a second embodiment of the present invention, all the control gates are set at the operational voltage from the beginning. In both embodiments, the bit line and word gate are used to address the selected memory cell.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: May 3, 2011
    Assignee: Halo LSI Inc.
    Inventors: Tomoko Ogura, Nori Ogura, Seiki Ogura, Tomoya Saito, Yoshitaka Baba
  • Patent number: 7447077
    Abstract: A reference circuit is described for creating a reference signal using a twin MONOS memory cell. A first portion of the twin MONOS memory cell connects to a charged and floating bit line a current source formed in a second portion of the twin MONOS cell that discharges the charged bit line to form a reference signal for a sense amplifier. The sense amplifier compares the reference signal to a signal from a selected memory cell upon which memory operations are being performed comprising read, erase verify and program verify.
    Type: Grant
    Filed: August 7, 2006
    Date of Patent: November 4, 2008
    Assignee: Halo LSI, Inc.
    Inventors: Tomoko Ogura, Nori Ogura, Seiki Ogura, Yoshitaka Baba
  • Patent number: 7411247
    Abstract: The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be fabricated to pull the electrons out through either the top or the bottom oxide layer of the ONO insulator. The device also incorporates a raised memory bit diffusion between the control gates to reduce bit resistance. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention.
    Type: Grant
    Filed: January 12, 2007
    Date of Patent: August 12, 2008
    Assignee: Halo LSI, Inc.
    Inventors: Seiki Ogura, Kimihiro Satoh, Tomoya Saito
  • Patent number: 7394703
    Abstract: The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be fabricated to pull the electrons out through either the top or the bottom oxide layer of the ONO insulator. The device also incorporates a raised memory bit diffusion between the control gates to reduce bit resistance. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention.
    Type: Grant
    Filed: April 21, 2006
    Date of Patent: July 1, 2008
    Assignee: Halo LSI, Inc.
    Inventors: Seiki Ogura, Kimihiro Satoh, Tomoya Saito
  • Patent number: 7391653
    Abstract: The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be fabricated to pull the electrons out through either the top or the bottom oxide layer of the ONO insulator. The device also incorporates a raised memory bit diffusion between the control gates to reduce bit resistance. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention.
    Type: Grant
    Filed: April 21, 2006
    Date of Patent: June 24, 2008
    Assignee: Halo LSI, Inc.
    Inventors: Seiki Ogura, Kimihiro Satoh, Tomoya Saito