Abstract: A method for manufacturing a trench MOSFET includes: forming a trench extending from an upper surface of an epitaxial layer of a first dopant type into the epitaxial layer; forming a gate dielectric layer and a gate conductor located in the trench; forming a body region of a second dopant type located in the epitaxial layer, where the body region is adjacent to the trench; forming a source region of the first dopant type located in the body region; forming a first dielectric layer on the source region and the gate dielectric layer; forming a contact hole extending through the first dielectric layer and the source region and extending into the body region; forming a spacer on a side wall of the contact hole; forming a body contact region of the second dopant type through the contact hole; and forming a conductive channel filling the contact hole.

Abstract: A method for manufacturing a trench field-effect transistor includes forming an epitaxial layer on a substrate; forming a trench in the epitaxial layer, forming a first insulating layer and a shielding conductor in the trench, where the first insulating layer surrounds the shielding conductor and partially fills the trench; forming a dielectric layer on the epitaxial layer, the first insulating layer, and a side wall of the trench; etching a part of the dielectric layer to form a dielectric region, where the dielectric region is located on the first insulating layer and the side wall of the trench; and forming a second insulating layer and a gate conductor in the trench, where the second insulating layer surrounds the gate conductor, fills the trench, and extends to the surface of the epitaxial layer.

Abstract: A method for manufacturing a MOSFET includes: forming a first trench and a second trench; forming a first shield gate dielectric layer and a first shielding conductor at a lower part of the first trench and a second shield gate dielectric layer and a second shielding conductor at a lower part of the second trench; forming a first dielectric interlayer and a second dielectric interlayer; forming a first gate dielectric layer and a first gate conductor at an upper part of the first trench and a second gate dielectric layer and a second gate conductor at an upper part of the second trench; and forming a body region, a source region, and a contact region. A dielectric constant of the second gate dielectric layer located in the second trench is greater than that of the first gate dielectric layer located in the first trench.

Abstract: Disclosed a silicon carbide MOSFET device and manufacturing method thereof. The method includes: forming a patterned first barrier layer on an upper surface of the substrate; forming a base region of a second doping type extending from the upper surface to an inside of the substrate through oblique implantation in a first ion implantation process by using a first barrier layer as a mask; forming a source region of the first doping type in the substrate; forming a contact region of the second doping type in the substrate; and forming a gate structure, an implantation angle of the first ion implantation process is adjusted so that the base region extends below a part of the first barrier layer. The method of the present disclosure not only reduces one photoetching process and saves cost, but also realizes a short channel and reduces an on-resistance of the device.

Abstract: A buck-boost converter includes a first switch connected between an input terminal that receives an input voltage and a first terminal of an inductor, a second switch connected between the first terminal of the inductor and an output terminal that outputs an output voltage, a third switch connected between a second terminal of the inductor and a ground terminal, and a fourth switch connected between the second terminal of the inductor and an inverting input terminal that receives an inverted input voltage obtained by inverting the input voltage.

Abstract: The present disclosure relates to a wafer level chip scale package with a rhombus shape which includes a semiconductor chip with a rhombus shape and a solder ball array including a plurality of solder balls formed on one surface of the semiconductor chip. Among four interior angles of the semiconductor chip, two of the four interior angles facing each other in a short diagonal direction are approximately 120°, and two of the four interior angles facing each other in a long diagonal direction are approximately 60°.

Abstract: A 3-level converter includes: an inductor connected in series between a switching node and an output terminal from which an output voltage is output, an output capacitor connected between the output terminal and a ground terminal, a first switch connected between an input terminal to which an input voltage is input and a top plate node, a second switch connected between the top plate node and the switching node, a third switch connected between the switching node and a bottom plate node, a fourth switch connected between the bottom plate node and a ground terminal, a flying capacitor connected between the top plate node and the bottom plate node, balancing switches connected between the switching node and a balancing node, a top balancing capacitor connected between the input terminal and the balancing node, and a bottom balancing capacitor connected between the balancing node and a ground terminal.

Abstract: A 3-level buck-boost converter includes: an inductor connected in series between a switching node and a ground terminal; an output capacitor connected between an output terminal from which an output voltage is output and a ground terminal; a first switch connected between an input terminal to which an input voltage is input and a top plate node; a second switch connected between the top plate node and the switching node; a third switch connected between the switching node and a bottom plate node; a fourth switch connected between the bottom plate node and the output terminal; a flying capacitor connected between the top plate node and the bottom plate node; balancing switches connected between the switching node and the balancing node; a top balancing capacitor connected between the input terminal and the balancing node; and a bottom balancing capacitor connected between the balancing node and the output terminal.

Abstract: An electromagnetic induction heating apparatus for heating an aerosol-forming article of an electronic cigarette includes: a power supply unit configured to supply DC power; a power amplifier including a switch unit composed of a pair of transistor switches having a differential structure and operating by receiving the DC power from the power supply unit, and a LC resonant network composed of a resonant inductor connected to an output terminal of the switch unit and electromagnetically inductively coupled with an inductor component of a heat-generating body for heating the aerosol-forming article of the electronic cigarette and a resonant capacitor connected in parallel to the resonant inductor; and a driving unit configured to adjust an operation of the power amplifier to adjust a temperature of the heat-generating body.

Abstract: An LDMOS transistor and a method for manufacturing the same are provided. The method includes: forming an epitaxial layer on a substrate, forming a gate structure on an upper surface of the epitaxial layer, forming a body region and a drift region in the epitaxial layer, forming a source region in the body region, forming a first insulating layer on the gate structure and an upper surface of the epitaxial layer and, forming a shield conductor layer on the first insulating layer, forming a second insulating layer covering the shield conductor layer, forming a first conductive path, to connect the source region with the substrate, and forming a drain region in the drift region. By forming the first conductive path which connects the source region with the substrate, the size of the LDMOS transistor and the resistance can be reduced.

Abstract: A super-junction VDMOS device with a low on-resistance includes: a super-junction structure disposed on a drain region; a super-junction structure having a first semiconductor pillar and a second semiconductor pillar. A HEMT structure having heterojunctions is formed between the first semiconductor pillar and the second semiconductor pillar. The HEMT structure includes a first semiconductor material pillar and a second semiconductor material pillar. Heterojunctions are formed in the super-junction structure to form the HEMT structure, inducing two-dimensional electronic gas to facilitate electrical conduction, such that the on-resistance of the VDMOS device is significantly reduced. The voltage difference between the first semiconductor pillar and the second semiconductor pillar in the super-junction structure is utilized to control a cutting-off behavior of the HEMT structure.

Abstract: A super-junction semiconductor device with an enlarged process window for a desirable breakdown voltage includes: a semiconductor substrate and an epitaxial layer deposited on the semiconductor substrate. The epitaxial layer includes a first semiconductor layer, and a second semiconductor layer disposed on the first semiconductor layer. A band gap of the first semiconductor layer is greater than a band gap of the second semiconductor layer. A super-junction structure is formed in the epitaxial layer, including at least one first epitaxial pillar of a first dopant type, and at least one second epitaxial pillar of a second dopant type. The first epitaxial pillar and the second epitaxial pillar are alternately arranged along a transverse direction. The epitaxial layer has a sandwich structure.

Abstract: A method of making a silicon carbide MOSFET device can include: providing a substrate with a first doping type; forming a patterned first barrier layer on a first surface of the substrate; forming a source region with a first doping type in the substrate; forming a base region with a second doping type and a contact region with a second doping type in the substrate, and forming a gate structure. The first barrier layer can include a first portion and a second portion, the first portion can include a semiconductor layer and a removable layer different from the semiconductor layer, and the second portion can only include the removable layer.

Abstract: A silicon carbide power semiconductor device is provided, including a substrate, a drift region, a body region, a source region, a base region, a shielding region, a JFET region, a gate structure, an insulating layer, and a source metal layer. The source contacting window has first edges within second edges of the body region corresponding to the first edges, and the source metal layer abuts only a part of the source region. The area of the silicon carbide power semiconductor device of the present disclosure is thus reduced. Therefore, the ratio of the channel length to the area of the silicon carbide power semiconductor device and the ratio of the area of the JFET region to the area of the silicon carbide power semiconductor device are increased, whereby the specific on-resistance of the silicon carbide power semiconductor device is reduced.

Abstract: A method of manufacturing a trench MOSFET can include: forming a trench extending from an upper surface of a semiconductor base layer to internal portion of the semiconductor base layer; forming a first insulating layer covering sidewall and bottom surfaces of the trench and the upper surface of the semiconductor base layer; forming a shield conductor filling a lower portion of the trench, where the first insulating layer separates the shield conductor from the semiconductor base layer; forming a second insulating layer covering a top surface of the shield conductor, where the first insulating layer separates the second insulating layer from the semiconductor base layer, and the first and second insulating layers conformally form a dielectric layer; and removing the dielectric layer located on the upper surface of the semiconductor base layer and located on the upper sidewall surface of the trench.

Abstract: A MOSFET is made by: forming a trench extending from an upper surface of a base layer to an internal portion of the base layer; forming a first insulating layer and a shield conductor occupying a lower portion of the trench; forming a gate dielectric layer and a gate conductor occupying an upper portion of the trench, where a top surface of the gate conductor is lower than the upper surface of the base layer; and before forming a body region, forming a blocking region on a region of the top surface of the gate conductor adjacent to sidewalls of the trench to prevent impurities from being implanted into the base layer from the sidewalls of the trench during subsequent ion implantation.

Abstract: An LDMOS transistor and a method for manufacturing the same are provided. The method includes: forming an epitaxial layer on a substrate, forming a gate structure on an upper surface of the epitaxial layer, forming a body region and a drift region in the epitaxial layer, forming a source region in the body region, forming a first insulating layer on the gate structure and an upper surface of the epitaxial layer and, forming a shield conductor layer on the first insulating layer, forming a second insulating layer covering the shield conductor layer, forming a first conductive path, to connect the source region with the substrate, and forming a drain region in the drift region. By forming the first conductive path which connects the source region with the substrate, the size of the LDMOS transistor and the resistance can be reduced.

Abstract: A LDMOS transistor and manufacturing method includes: forming an epitaxial layer on a substrate of a first doping type; forming a gate structure on an upper surface of the epitaxial layer; forming a source region of a second doping type in the epitaxial layer, the second doping type is opposite to the first doping type; forming a patterned first insulating layer on the upper surface of the epitaxial layer and the gate structure, and at least exposes part of the source region; forming a first conductive channel by using a sidewall as a mask, the first conductive channel extends from the source region to an upper surface of the substrate so as to connect the source region with the substrate; and forming a drain region of the second doping type in the epitaxial layer.