Abstract: A package for a device comprises a header having a substantially flat upper surface. An insulating disk is affixed to the upper surface of the header for having the device mounted thereon. A barrel having upper and lower portions of respectively greater and smaller diameters, and having a step between the diameters, has a lower edge thereof attached to the upper surface of the header so as to surround the disk. A ceramic lid in the upper portion of the barrel abuts the step is attached thereat.

Abstract: A packaging assembly for electrical components includes a heat sink having a mounting surface upon which certain ones of the electrical components are mounted. An associated lead frame is rigidly secured to an edge of the heat sink, and one or more extended ends of selected leads thereof are formed into mounting pads positioned over the mounting surface of the heat sink for receiving other ones of the electrical components. Dielectric material is positioned between the mounting pads and the heat sink, for electrically isolating the electrical components mounted upon the mounting pads from one another and from electrical components mounted directly on the heat sink. The electrical components and proximate ends of the leads of the lead frame are electrically interconnected via electrical conductors, and the assembly is encapsulated with a plastic material about the heat sink and proximate ends of the lead frame, whereafter bridge elements between the leads of the lead frame are severed.

Abstract: An hermetically sealed package for a die comprised of a base plate, a side wall mounted on the brace plate, a printed circuit board connecting terminals on one side of the die to a first lead, connector clips connecting terminals on the other side of die to a bus having posts extending, wires connecting other terminals on the other side of the die to runners on the circuit board, leads respectively extending from each runner, a cover lid hermetically sealed to the side wall, the lid having openings hermetically sealed by insulators having slots through which the leads respectively extend in sealed relationship.

Abstract: The present invention relates to a power MOS transistor having a current limiting circuit incorporated in the same substrate as the transistor. The power MOS transistor includes a drain region extending through the substrate between opposed first and second surfaces, a plurality of body regions in the substrate at the first surface, a separate source region in the substrate at the first surface within each body region and a channel extending across each body region between its junction with its respective source region and its junction with the drain region. A conductive gate is over and insulated from the first surface and extends over the channel regions. A first conductive electrode extends over and is insulated from the gate and contacts a first portion of the source regions. A second conductive electrode extends over and is insulated from the gate and contacts a second portion of the source regions. The second portion contains a smaller number of the source regions than the first portion.

Abstract: There is disclosed a decoder configuration for a high-speed flash-type analog-to-digital converter which utilizes a plurality of comparators arranged from a first lower order comparator to a last high order comparator based on the particular position of each comparator as coupled to taps of a reference resistance ladder. The measurement point in such a system can be logically decoded by establishing the tap where all comparators below it are low and ideally all comparators above the tap are high. This is implemented in a decoding scheme which implements the test by testing all combinations of three adjacent comparators so that the selected tap is high and the taps immediately above and below it are high and low respectively to therefore detect an HHL sequence. In regard to the present invention, there are included means which will prevent a higher order HHL sequence from appearing when a lower order HHL sequence is detected.

Abstract: A variable impedance element which is utilized to shunt a signal and control the amplitude of the signal utilizes a P-MOS and an N-MOS transistor operated in parallel. Separate control voltages are applied to each device in a direction to lower the impedance of the device with an increase in the peak to peak voltage of the input signal. Thus, by controlling each of the separate shunted transistors from separate peak detectors and according to the polarity of the signal voltage, each transistor will operate somewhat independent from the other to therefore provide accurate gain control and a symmetrical impedance variation.

Abstract: By comparing the distorted image of an edge pattern, such as a checker board pattern, reflected from the surface of a work piece, such as a silicon wafer, and received by a solid state television camera, with a similar image, reflected from the optically flat surface of a calibration piece substituted for the work piece, surface height irregularities, such as warpage, of the work piece can be measured with a high sensitivity and a large dynamic range at relatively low cost.

Abstract: A hybrid 2-D digital convolver in a video image processor to enhance or supress image characteristics comprises a rectangular array of delay elements of pixel duration arranged in rows and columns. A digital serial stream of data encoding pixel values of a 2-D image is coupled to successive rows of delay elements of the array in horizontal-line lengths. The pixel values are modified in a multiplier of preselected weight in series with the input of each columnar delay element in a row. An adder connected between pixel delay elements in each row combines weighted inputs and outputs from prior delay elements. The output of the last delay element of each row is combined with the row outputs of prior rows and the output of the adder following the output of the last delay element off the last row forms the processed output of the convolver. The arrangement of adders and delay elements in each row avoids cumulative adder delays and thereby improves image processing efficiency.

Abstract: A truncated product partial canonical signed digit (PCSD) multiplier is disclosed for use in a finite impulse response (FIR) digital filter. Each multiplier quantity is coded as two non-zero signed digits in an 8-bit word. Each non-zero signed digit is recoded into a four bit nibble for application to the multiplier. Each partial product output of the multiplier is truncated from 16 to 11 bits. The multiplier operations are performed in the sequence shift right, truncate, one's complement, add partial products and, according to the output of a logic control circuit, add one into an appropriate order.

Abstract: An adaptive digital filter can be implemented on a single Very Large Scale Integrated (VLSI) circuit silicon chip and the Least Mean Square adaptive filter algorithm can be performed by parallel processing during a single clock cycle. The adaptive filter contains dual delay lines to yield a sequence of simultaneous samples of both input and output signals. Correlations of the present error difference with previous samples of both input and output signals can then take place simultaneously in each clock cycle. The adaptive filter is modular and can be cascaded with other identical filters to form a high-order filter.

Abstract: Damping resistance is introduced via transformer coupling into a circuit which includes an inductance-capacitance (LC) filter arrangement to smooth the current pulses applied to a load.

Abstract: Integral linearity error in the operating characteristics of an analog to digital converter employing sampling comparators is reduced by recurrently connecting at least one resistive shunt across a predetermined central portion of a reference voltage divider input to the comparators. The shunt resistance is approximately an order of magnitude larger than the resistance of the shunted part of the divider. Each recurrent connection interval is of fixed duration independent of sampling rate, and each interval spans the beginning of a recurrent time of connection of said divider to said comparators.

Abstract: The accuracy of a bandgap type reference voltage generator which contains bipolar load elements is increased by the use of current compensation circuitry which includes a dummy load element which is the electrical equivalent of the load elements of the generator, an operational amplifier and a current mirror. The operational amplifier and the current mirror act to cause the same potential level (voltage) to be applied to the dummy load element as is applied to the load elements of the generator. A master leg of the current mirror generates a first output current which is identical to the current drawn by the load elements of the generator and provides the current to the dummy load element. A slave leg of the current mirror generates a second output current which is identical to the first output current and which is coupled to the load elements of the generator. Thus current used to drive the load elements of the generator is supplied by the compensation circuitry.

Abstract: There is disclosed a high-speed decoding apparatus for use in a flash-type analog-to-digital converter. The apparatus disclosed employs an OR gate which follows an AND gate which AND gate is conventionally employed in a comparator associated with such a converter. The OR gate functions to block any dynamic movement of the unknown input voltage from being transferred to the decode lines of the analog-to-digital converter. To further gain speed, autozeroed inverters are coupled to the output of the OR gate to further assure that the decoder lines are rapidly driven to therefore gain an extra advantage in high-speed operation of the converter employing the apparatus as described.

Abstract: Circuits embodying the invention include apparatus for sensing the amplitude and the frequency of the signals received from one section of a telephone cable and for propagating onto the succeeding section of telephone cable only those received signals having an amplitude greater than a predetermined level and whose frequency is within the predetermined range.

Abstract: An ion implantation apparatus includes an ion source, ion analyzer, ion acceleration means and ion deflection means interconnected in a sequential manner, but excludes a variable slit shutter as a means for attenuating the ion beam. A controllable source of inactive diluent gas is interconnected so as to provide a means for selecting the concentration of ions provided by the ion source to the ion analyzer.

Abstract: Programmable monolithic integrated circuit current mirrors configured as either current sources or current sinks include mixed MOS and bipolar technology on a substrate, wherein the master and slave elements each include a silicon-based emitter resistor having a positive temperature coefficient matched to the negative temperature coefficient of the V.sub.be of an associated bipolar transistor, for making the ratios of the master element current to the individual slave element currents substantially insensitive to dynamic temperature gradients produced in the associated substrate. Each slave is independently and individually compensated.

Abstract: A CMOS fractional reference source or voltage divider circuit includes a string (chain) of CMOS pairs of transistors connected with their source-drain circuits in series and with ends of the string being connected across an input power (voltage) supply. The P-channel transistors are all matched to one another in a one to one ratio, the N-channel transistors are all similarly matched to one another. Output terminals are connected at the nodes between pairs of transistors. Accurate tracking of the voltage of the power supply is achieved by connecting each gate of the chain in a manner to insure the same source-to-gate voltage on each transistor of the pair. In the preferred form, the string comprises two pairs of CMOS transistors and the voltage appearing at the output terminal thereof is equal to one half of the voltage of the power supply.

Abstract: A digital to analog converter including an R-2R ladder network receives digitally encoded sample signals in parallel through a set of chains of transistor switches, each chain having equal delay. The ladder network output impedance matches the characteristic impedance of a coaxial cable transmission line that couples the converter output to a utilization circuit. Output resistances of the switches which are connected to ladder network rung circuits are scaled in accordance with a predetermined algorithm to maintain symmetry of parallel connected resistive branches of the latter network seen at each rail terminal of the ladder. Three of the most significant bits of each input binary coded work are decoded to a bar code format before being coupled through the set of switch chains.

Abstract: A binary tree is created from flat part list and synonym output files and a component library. Each tree record includes a part, type, full path name, and net functional description for each primary net of each block and for each component in that block. The hierarchical coupling of these records and the primary net descriptions in each record supply all of the information necessary to extract a hierarchical net list.