Abstract: A semiconductor memory device comprises a memory cell array including a plurality of memory cells, a word line selection circuit for selecting a word line, a bit line selection circuit for selecting a bit line, an input/output circuit for supplying data to be written to a selected memory cell via the selected bit line and for reading data from the selected memory cell via the selected bit line, a word line driver including a MOS transistor having a drain supplied with a supply voltage and a source connected to the word line selection circuit for supplying a word line voltage to the selected word line via the word line selection circuit, a word line boosting circuit connected to the drain of the MOS transistor for boosting the word line voltage via the MOS transistor, a boosting capacitor connected across the source and the gate of the MOS transistor, and a clamping circuit connected to the gate of said MOS transistor for clamping the voltage level at a predetermined level.