Abstract: An improved input/output FIFO buffering device with expanded buffers for a universal asynchronous receiver/transmitter (UART) that includes scalable trigger levels for generation of an external service request is disclosed. Standard selectable trigger levels used in a type 16550 UART are provided as well as expanded scalable trigger levels to accommodate the larger buffers. The larger scalable trigger levels may be employed in a manner transparent to an application written for 16 byte buffers so as to physical accommodate higher data rates without requiring applications to know that more buffer space is used. A reinterruptable timer inhibits generation of an interrupt service request until a predetermined period of time after the most recent interrupt request has been serviced. The period of the timer is selectively programmable.

Abstract: A modem (20) receiving high speed digital data from data terminal equipment (10). The modem operates in a "software UART" state when in command mode. A high speed clock (30) is used to continually take samples of an incoming signal from a DTE (10). A microprocessor (40) multitasks between analyzing the samples taken from the incoming signal and generating output signals to be sent to the DTE (10). The high speed clock is adjustable, setting the sample rate to be a integer multiple of at least eight times all the possible bit rates of the incoming signal. This permits quicker autobauding. Commands and prefixes can be received and detected simultaneously with the transmission of result codes to previous commands.

Abstract: A real-time method for improving data compression. The correlation between data characters being provided a modem (10) is determined. Two measures are used to determine the correlation between data characters: the shape of tree(s) (6) in encoding table (16) and the compression ratio (96). Once the correlation between data characters is determined using the two measures, the size of the encoding table (16) can be changed. If the data characters are not correlated, meaning the data is random or pseudo-random, the size of the encoding table is decreased. If the data characters are highly correlated, changing the size of the encoding table reduces time spent attempting to compress incompressible data and increases data compression for compressible data.

Abstract: A method for detecting high speed data received by a computer and for delaying displaying the receive data, thereby increase the microprocessor time devoted to receiving and storing the input data. Three parameters are utilized for determining when updating the display should be delayed because data input speed is high. First, if the input data is close to filling the computer's receive buffer, the data input speed is high. Second, if the data input port becomes idle, no more data is being input to the computer and the display may be updated. Third, if the display has not been updated recently, as indicated by a preset timer timing out, an update of the display is forced so that the user can verify that data is successfully being input. By varying and limiting the number of display updates, the microprocessor is allocated more time to store and process received data when the data input speed demands.

Abstract: Method and apparatus for reducing latency delay associated with converting asynchronous, serial digital data to packet data. The number of data characters received before a time-out occurs are counted; the last character received before a time-out occurs is recognized; or the number of data characters transmitted before a signal is received from the destination terminal are counted. The information thus gathered is used to predict the occurrence of future latency delay. Data packets are transmitted immediately upon the subsequent receipt of a number of data characters equal to the number of data characters received before the time-out occurred; receipt of a character identical to the last character received before a time-out; or receipt of a number of data characters equal to the number of data characters transmitted before another signal is received from the destination terminal, respectively. By transmitting immediately when a latency delay is expected, the latency delay is completely avoided.

Abstract: A status word modification device. A serial communications device (11) contains two universal asynchronous receiver transmitters (UARTs) (14, 15). Each UART contains a first in, first out (FIFO) buffer (14a), two status buffers (14b, 14c), and a FIFO control register (14d). If the applications program in the host (10) is an enhanced application program which supports the use of the FIFO buffer (14a), then the program will cause FIFO enablement instructions to be written into the control register (14d). In this case, the interface circuit (22) allows the status words to pass unaltered whenever the host (10) reads the status buffers (14b, 14c). However, if the applications program is a standard applications program which does not support the use of the FIFO buffer (14a), then the program will not write to the control register (14d).

Abstract: A data flow controller (150) for monitoring and automatically controlling the flow of serial data from a remote transmitter to a host device. A serial communications card (11) provides an interface between a remote transmitter connected to a serial port connector (20) and a host device (10). The card (11) contains a UART (14) which has a buffer. A counter (151) counts the number of bytes received by the UART (14) since the last time that the host (10) read all the data in the buffer. If the number exceeds a predetermined portion of the buffer capacity the counter output (Q11) will go high, thereby disabling the counter and sending a control signal (DTR, RTS) to the remote transmitter to stop sending data. Once the host (10) has read all the data in the buffer the UART (14) provides a signal (-RXREADY) which resets the counter (151), thereby causing the output (Q11) to go low, thereby allowing the remote transmitter to resume sending data.

Abstract: A bus access controller. An interface circuit (22) controls the access of a host computer (10) and a microprocessor (23) to one or more UARTs (14, 15). The microprocessor (23), which has no provision for waiting for a data transfer, is required to provide a signal of its intent to perform a data transfer prior to beginning the actual data transfer. The signal is identical to the actual data transfer operation. If the host (10) attempts a data transfer operation while the microprocessor (23) is conducting a data transfer operation, or if the host data transfer cannot be completed prior to the time that the microprocessor data transfer will commence, then the interface circuit (22) signals the host (10) that the data transfer will take additional time by deasserting the I/O READY line (12a). Once the microprocessor data transfer is completed then the I/O READY signal is reasserted and the host data transfer is completed.

Abstract: An improved rack assembly is provided which includes an improved configuration for mounting multiple enclosed circuit boards. The rack assembly includes improvements in heat sinking power supplies incorporated within the assembly, relative adjustability of various elements of the rack after assembly, and ventilation of the rack during operation in an efficient manner.

Abstract: A DSP receiver for a fast turnaround modem, particularly suited for a half duplex fast turnaround modem which prevents destruction of communication channel related adaptive equalizer parameters upon loss of carrier. Upon detection of carrier loss, after sufficient time has been allowed for the last informational data bits to pass through the receiver's adaptive equalizer, the output of the equalizer's FIR filter delay line is looped back, via a multiplexer, to the input of the equalizer so that communications channel related samples are continuously provided to the equalizer to maintain the parameters at values based on the receiver's actual experience with data transmitted through the communications channel to which it is connected. A delay timer responsive to the loss of carrier signal will terminate updating of the adaptive equalizer parameters a predetermined time after loss of carrier. Alternately, detection of a standard end of data flag in the data stream will also terminate parameter update.