Abstract: A semiconductor memory device includes a bottom electrode, a magnetic tunnel junction (MTJ) structure disposed over the bottom electrode, a seed layer disposed between the MTJ structure and the bottom electrode, and a non-magnetic amorphous insertion layer disposed between the seed layer and the bottom electrode.

Abstract: A one-time programmable memory unit cell includes a substrate comprising thereon a first active area and a second active area isolated from the first active area, a read select transistor disposed on the first active area, a data storage transistor disposed on the first active area and serially connected to the read select transistor, and a program select transistor disposed on the second active area. During read operation, the state “1” bit current is the transistor “on” current, while the state “0” bit current is the transistor “off” current.

Abstract: A semiconductor memory device includes a substrate; a film stack on the substrate; a silicon device layer on the film stack; and a trench with corrugated sidewall surface extending into the silicon device layer, the film stack, and the substrate. A trench capacitor is located in the trench. The trench capacitor includes an inner electrode and an outer electrode with a node dielectric layer therebetween. The node dielectric layer is in direct with the film stack and the bulk semiconductor substrate. A transistor is disposed on the substrate. The transistor includes a source region and a drain region, a channel region between the source region and the drain region, and a gate over the channel region. The source region is electrically connected to the inner electrode of the trench capacitor.

Abstract: A magnetic tunnel junction (MTJ) element including a free layer, a reference layer; and a tunnel barrier layer between the free layer and the reference layer. The reference layer includes a first pinned layer, a second pinned layer, an anti-ferromagnetic coupling (AFC) spacer layer between the first pinned layer and the second pinned layer, a first spacer layer adjacent to the second pinned layer, a second spacer layer, a ferromagnetic layer sandwiched by the first spacer layer and the second spacer layer, a polarization enhancement layer adjacent to the second spacer layer.

Abstract: A semiconductor structure includes a substrate having a doped silicon substrate, a buried oxide layer, and a silicon device layer. A trench capacitor having an inner electrode and a node dielectric layer is formed in a trench of the substrate. The inner electrode and the node dielectric layer extend into the doped silicon substrate. A select transistor is disposed in the silicon device layer. An embedded contact is disposed atop the trench capacitor to electrically couple a doped region of the select transistor with the inner electrode. A first dielectric layer is disposed around the select transistor. A second dielectric layer is deposited on the first dielectric layer. A contact plug is formed in the second dielectric layer and the first dielectric layer and is in direct contact with the embedded contact. A memory stack with a MTJ element is disposed on the contact plug.

Abstract: A method of forming a plug for a semiconductor device and a semiconductor device thereof are disclosed. The proposed method of forming a plug for a semiconductor device, wherein the semiconductor device includes a deep trench (DT) structure and a storage node configured in the DT structure, comprising: (a) filling a single film in the DT structure and to cover the storage node; and (b) etching back the single film to form the plug located in the DT structure and around the storage node, wherein the single film forms a liner of a single type.

Abstract: A method for forming a semiconductor device is disclosed. A substrate having a semiconductor substrate, an insulator layer on the semiconductor substrate, and a silicon device layer on the insulator layer is provided. At least one capacitor cavity with corrugated sidewall surface is formed within the insulator layer between the semiconductor substrate and the silicon device layer. At least one buried capacitor is formed in the at least one capacitor cavity. The at least one buried capacitor comprises inner and outer electrodes with a capacitor dielectric layer therebetween. At least one transistor is formed on the substrate. The at least one transistor comprises a source region, a drain region, a channel region between the source region and the drain region, and a gate over the channel region. The source region is electrically connected to the inner electrode of the at least one buried capacitor.

Abstract: A method for forming a magnetic memory device is disclosed. At least one magnetic tunneling junction (MTJ) stack is formed on the substrate. The MTJ stack comprises a reference layer, a tunnel barrier layer and a free layer. A top electrode layer is formed on the MTJ stack. A patterned sacrificial layer is formed on the top electrode layer. The MTJ stack is then subjected to a MTJ patterning process in a high-density plasma chemical vapor deposition (HDPCVD) chamber, thereby sputtering off the MTJ stack not covered by the patterned sacrificial layer. During the MTJ patterning process, sidewalls of layers or sub-layers of the MTJ stack are simultaneously passivated in the HDPCVD chamber by depositing a sidewall protection layer.

Abstract: A storage layer of a magnetic tunnel junction (MTJ) element is disclosed. The storage layer having perpendicular magnetic anisotropy includes a first ferromagnetic layer, a first dust layer disposed directly on the first ferromagnetic layer, a second ferromagnetic layer disposed directly on the first dust layer, a second dust layer disposed directly on the second ferromagnetic layer, and a third ferromagnetic layer disposed directly on the second dust layer. A material of the first dust layer is different from a material of the second dust layer.

Abstract: A method for fabricating a magnetic tunneling junction (MTJ) element is disclosed. A substrate is provided. A reference layer is formed on the substrate. A tunnel barrier layer is formed on the reference layer. A free layer is formed on the tunnel barrier layer. A composite capping layer is formed on the free layer. The composite capping layer comprises an amorphous layer, a light-element sink layer, and/or a diffusion-stop layer. The reference layer, the tunnel barrier layer, the free layer, and the composite capping layer constitute an MTJ stack.

Abstract: A physically unclonable function (PUF) circuit includes a program control transistor, a program select transistor, a read select transistor, and a PUF bit storage transistor. The PUF bit storage transistor has a drain region coupled to the read select transistor, a source region coupled to a source line and the program select transistor, a channel region, a gate dielectric layer, and a gate electrode coupled to the program select transistor. The gate dielectric layer has a first portion formed on the drain region, a second portion formed on the source region, and a main portion formed on the channel region and between the first portion and the second portion, thicknesses of the first portion of the gate dielectric layer and the second portion of the gate dielectric layer being smaller than a thickness of the main portion of the gate dielectric layer.

Abstract: A semiconductor memory device includes at least an OTP cell having a transistor and a PN junction diode. The OTP cell further includes a substrate having a first conductivity type, and a source and a drain in the substrate. The source includes a source doping region having the first conductivity type. The drain includes a drain doping region having a second conductivity type opposite to the first conductivity type. A gate is disposed on the substrate between the source and the drain. The source further includes a pocket doping region having the second conductivity type under the gate. The pocket doping region and the source doping region constitute the PN junction diode.

Abstract: A method for forming a semiconductor device is disclosed. A substrate having a semiconductor substrate, an insulator layer on the semiconductor substrate, and a silicon device layer on the insulator layer is provided. At least one capacitor cavity with corrugated sidewall surface is formed within the insulator layer between the semiconductor substrate and the silicon device layer. At least one buried capacitor is formed in the at least one capacitor cavity. The at least one buried capacitor comprises inner and outer electrodes with a capacitor dielectric layer therebetween. At least one transistor is formed on the substrate. The at least one transistor comprises a source region, a drain region, a channel region between the source region and the drain region, and a gate over the channel region. The source region is electrically connected to the inner electrode of the at least one buried capacitor.

Abstract: A semiconductor memory structure includes a substrate, a magnetic tunneling junction (MTJ) stack disposed on the substrate, and an encapsulation layer surrounding the MTJ stack. The encapsulation layer comprises an outer silicon oxynitride layer with a composition of SiOx1Ny1 and an inner silicon oxynitride layer with a composition of SiOx2Ny2, wherein x1/y1>x2/y2.

Abstract: A stacked capacitor includes a substrate having a first ILD layer thereon and a source conductive plate in the first ILD layer; a second ILD layer disposed on the first ILD layer; and a stacked capacitor area in the second ILD layer. The stacked capacitor area partially exposes the source conductive plate. A fin-shaped structure is disposed on the source conductive plate within the stacked capacitor area. The fin-shaped structure includes horizontal fins and vertical fins. A widened central hole penetrates through the fin-shaped structure and partially exposes the source conductive plate. A first conductive layer is disposed on the fin-shaped structure and the source conductive plate in the widened central hole. A capacitor dielectric layer is disposed on the first conductive layer. A second conductive layer is disposed on the capacitor dielectric layer.

Abstract: A semiconductor device and methods thereof are disclosed. The proposed semiconductor device includes at least a unit cell wherein the unit cell includes a select transistor, and half of a ground-gate transistor electrically connected to the select transistor, and including a central conductive gate electrode region, two side conductive spacer regions and a gate dielectric layer, wherein a first and a second thicknesses of the gate dielectric layer underneath the two side conductive spacer regions are thinner than a third thickness of the gate dielectric layer underneath the central conductive gate electrode region.

Abstract: A semiconductor device includes a substrate having a semiconductor substrate, an insulator layer on the semiconductor substrate, and a silicon device layer on the insulator layer. At least one capacitor cavity with corrugated sidewall surface is disposed within the insulator layer between the semiconductor substrate and the silicon device layer. At least one buried capacitor is provided in the at least one capacitor cavity. The at least one buried capacitor includes an inner electrode and an outer electrode with a capacitor dielectric layer therebetween.

Abstract: A semiconductor device for a volatile memory is disclosed. The semiconductor device includes a substrate, a side wall and an epitaxial liner. The substrate has a first height and is made of a first material having a first lattice parameter. The side wall defines a deep trench. The epitaxial liner is disposed around the side wall, is made of a second material having a second lattice parameter, and has a second height having a same level with the first height, wherein the epitaxial liner and the side wall cooperate for creating a desired aspect ratio for the deep trench.

Abstract: A method for forming a magnetic memory device is disclosed. At least one magnetic tunneling junction (MTJ) stack is formed on the substrate. The MTJ stack comprises a reference layer, a tunnel barrier layer and a free layer. A top electrode layer is formed on the MTJ stack. A patterned sacrificial layer is formed on the top electrode layer. The MTJ stack is then subjected to a MTJ patterning process in a high-density plasma chemical vapor deposition (HDPCVD) chamber, thereby sputtering off the MTJ stack not covered by the patterned sacrificial layer. During the MTJ patterning process, sidewalls of layers or sub-layers of the MTJ stack are simultaneously passivated in the HDPCVD chamber by depositing a sidewall protection layer.

Abstract: A semiconductor memory device includes a substrate; a film stack on the substrate; a silicon device layer on the film stack; and a trench with corrugated sidewall surface extending into the silicon device layer, the film stack, and the substrate. A trench capacitor is located in the trench. The trench capacitor includes an inner electrode and an outer electrode with a node dielectric layer therebetween. The node dielectric layer is in direct with the film stack and the bulk semiconductor substrate. A transistor is disposed on the substrate. The transistor includes a source region and a drain region, a channel region between the source region and the drain region, and a gate over the channel region. The source region is electrically connected to the inner electrode of the trench capacitor.