Abstract: A power-supply control device and a power test system are disclosed. The power test system includes a memory and a processor. The processor is configured to: obtain at least one power-supply path manner of at least one power-down test device; determine at least one power-supply path interface according to the at least one power-supply path manner; determine at least one electronic switch according to the at least one power-supply path interface; determine at least one target device to be tested; obtain at least one power-down test instruction according to the at least one target device; establish a target power-supply path corresponding to the target device between the at least one power-supply path interface and the at least one electronic switch according to the power-supply path establishment parameter; and at the target power-supply path, perform a power-down operation according to the power-down execution parameter.

Abstract: A memory control method, a memory storage device and a memory control circuit unit are provided. The method includes: setting preset read count thresholds corresponding to physical erasing units respectively; in a background operation, in response to a read count of a first physical erasing unit in the physical erasing units being greater than its corresponding preset read count threshold, reading word lines in the first physical erasing unit to obtain first error bit amounts; determining whether a refresh operation needs to be performed on the first physical erasing unit according to first error bit amounts; in response to no need to perform the refresh operation on the first physical erasing unit, selecting a first word line with the largest first error bit amount in the word lines, and detecting a voltage distribution variation of the first word line; and calculating a new read count threshold of the first physical erasing unit according to the voltage distribution variation.

Abstract: A performance match method of memory, a memory storage device and a memory control circuit unit are disclosed. The method includes: receiving a performance match command from a host system; in response to the performance match command, adjusting an operation setting of a memory storage device to match a performance of the memory storage device with a performance requirement of the host system; and interacting with the host system based on the adjusted operation setting.

Abstract: A memory polling method, a memory storage device and a memory control circuit unit are provided. The memory polling method includes: detecting a plurality of busy times corresponding to a plurality of physical units when executing a plurality of first commands; counting the busy times corresponding to the physical units to generate a count statistic value, and determine a delay time based on the count statistic value; and transmitting a plurality of status requests to a rewritable non-volatile memory module after the delay time.

Abstract: A valid node management method, a memory storage device and a memory control circuit unit are disclosed. The method includes: establishing a valid node management table corresponding to a first physical management unit; storing valid node management data in the valid node management table, wherein the valid node management data reflects a distribution status of a valid node in the first physical management unit; receiving an operation command from a host system, wherein the operation command is configured to change a data storage status of the first physical management unit; and updating the valid node management data in the valid node management table in response to the operation command.

Abstract: A mapping table updating method, a memory storage device and a memory control circuit unit are disclosed. The method includes: receiving, a plurality of operation commands from a host system; performing a first table updating operation according to a first operation command and a third operation command among the operation commands to read and update a first sub-mapping table and a third sub-mapping table from a rewritable non-volatile memory module; and after the first table updating operation is finished, performing a second table updating operation according to a second operation command among the operation commands to read and update a second sub-mapping table from the rewritable non-volatile memory module.

Abstract: A memory operation control method, a memory storage device, and a memory control circuit unit are disclosed. The method includes the following. Management data is established, which includes status recording data. First status information corresponding to a first physical unit is stored in the status recording data. An operation command is received from a host system. The management data is queried according to the operation command. Whether to allow an execution of the operation command on the first physical unit is determined according to a query result.

Abstract: A mapping table updating method, a memory storage device and a memory control circuit unit are disclosed. The method includes: receiving, a plurality of operation commands from a host system; performing a first table updating operation according to a first operation command and a third operation command among the operation commands to read and update a first sub-mapping table and a third sub-mapping table from a rewritable non-volatile memory module; and after the first table updating operation is finished, performing a second table updating operation according to a second operation command among the operation commands to read and update a second sub-mapping table from the rewritable non-volatile memory module.

Abstract: A data arrangement method based on file system, a memory storage device and a memory control circuit unit are disclosed. The method includes: analyzing a file system stored in a system region to obtain a plurality of first logical units to which a first file belongs and first distribution information of a plurality of first physical units in a storage region, wherein the first physical units are mapped by the first logical units; determining whether to activate a data arrangement operation on the first file according to the first distribution information; after the data arrangement operation on the first file is activated, reading first data belonging to the first file from the first physical units; and writing, sequentially, the read first data to at least one second physical unit in the storage region.

Abstract: A performance match method of memory, a memory storage device and a memory control circuit unit are disclosed. The method includes: receiving a performance match command from a host system; in response to the performance match command, adjusting an operation setting of a memory storage device to match a performance of the memory storage device with a performance requirement of the host system; and interacting with the host system based on the adjusted operation setting.

Abstract: A data writing method, a memory storage device, and a memory control circuit unit are disclosed. The method includes the following. A write command is received from a host system. The write command instructs storing of first data belonging to a first logical unit. In response to the first data being first type data, the first data is stored in a first type physical unit according to the write command and first count information corresponding to a first logical range is updated. The first logical unit belongs to the first logical range. In response to the first count information meeting a preset condition, the first data is moved from the first type physical unit to a second type physical unit.

Abstract: A valid node management method, a memory storage device and a memory control circuit unit are disclosed. The method includes: establishing a valid node management table corresponding to a first physical management unit; storing valid node management data in the valid node management table, wherein the valid node management data reflects a distribution status of a valid node in the first physical management unit; receiving an operation command from a host system, wherein the operation command is configured to change a data storage status of the first physical management unit; and updating the valid node management data in the valid node management table in response to the operation command.

Abstract: A memory management method for a memory storage device is provided. The memory management method includes: detecting effective information of at least one operation event performed by the memory storage device in a first mode; and adjusting a threshold value according to the effective information. The threshold value is configured to determine whether to instruct the memory storage device to enter the first mode.

Abstract: A memory adaptive temperature controlling method, a storage device, and a control circuit unit are provided. In this exemplary embodiment, the temperature value is obtained according to the temperature measured by the thermal sensor, and the access speed to be reached is calculated according to the temperature change rate within the specific time range and the adjustment percentage when it is determined that the speed-down or speed-up operation is required to be performed. By adjusting the access speed of the memory storage device in a stepwise manner, the temperature of the memory storage device may be stabilized, thereby striking the balance between the temperature stability and the system performance of the memory storage device.

Abstract: A mapping table re-building method, a memory storage device and a memory control circuit unit are disclosed. The method includes: receiving write command from a host system, wherein the write command instructs storing first data to a first logical unit; performing a programming operation according to the write command to store the first data and identification information of the first logical unit to a first physical unit; updating a mapping table in response to the programming operation; detecting a table abnormal event related to the mapping table; reading the identification information of the first logical unit from the first physical unit in response to the table abnormal event; and re-building the mapping table according to the identification information of the first logical unit.

Abstract: A data storing allocation method, a memory storage apparatus, and a memory control circuit unit are provided. The method includes the following. A plurality of data writing speeds of a plurality of memory units are detected. An initial write volume of each memory unit is determined according to a number of dies in each memory unit. At least one compensation data volume is calculated according to the data writing speeds and the initial write volume of each memory unit. A write data corresponding to a write command is written to the memory units according to the initial write volume of each memory unit and the at least one compensation data volume.

Abstract: A table management method, a memory storage device and a memory control circuit unit are disclosed. The method includes: storing multiple table groups, wherein each of the table groups includes multiple voltage management tables; detecting a status of the memory storage device; determining one of the table groups as a target table group according to the status of the memory storage device, wherein the target table group includes multiple target voltage management tables; reading data from a rewritable non-volatile memory module by using at least one read voltage level according to at least one of the target voltage management tables.

Abstract: A write control method based on write behavior prediction, a memory storage device, and a memory control circuit unit are provided. The method includes: monitoring a first data write behavior of a host system during a first time range; according to the first data write behavior, predicting a second data write behavior of the host system during a second time range; obtaining a first measurement parameter and a first target parameter corresponding to the first data write behavior; according to the first measurement parameter, the first target parameter, and the second data write behavior, determining a write control parameter; and sending a write command sequence according to the write control parameter to instruct a rewritable non-volatile memory module to perform a data write based on multiple write modes during the second time range.

Abstract: A timer calibration method and an electronic device are disclosed. The method includes: performing a fitting operation according to a clock frequency of a clock device and an output of a timer to generate a fitting function; obtaining a first value output by the timer; and adjusting the first value to be a second value according to the fitting function to calibrate the timer.

Abstract: A memory management method, a memory storage device and a memory control circuit unit are disclosed. The method includes: performing a first write operation to store first data to a first physical unit; recording first unit management information corresponding to the first write operation, wherein the first unit management information reflects a usage order of first used physical units, and the first used physical units include the first physical unit; performing data merge operation to copy at least a part of data stored in the first physical unit to a second physical unit; and after the data merge operation is performed, recording second unit management information according to the first unit management information, wherein the second unit management information reflects a usage order of second used physical units. The second used physical units include the second physical unit but do not include the first physical unit.